Datapath synthesis for standard-cell design

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2009, Pages 207-211

  Zimmermann, Reto ^a  

^a SYNOPSYS SWITZERLAND LLC   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC OPERATIONS; CELL-BASED; CIRCUIT ARCHITECTURES; CIRCUIT IMPLEMENTATION; DATA PATHS; NETLIST; OPTIMIZATION STRATEGY; PERFORMANCE CHARACTERISTICS; RTL CODES; STANDARD CELL DESIGN; SYNTHESIS TOOL; TECHNIQUES USED;

TIMING CIRCUITS;

EID: 70350749455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARITH.2009.28     Document Type: Conference Paper

References (9)

1. R. Zimmermann and D. Q. Tran, "Optimized Synthesis of Sum-of-Products", 37th Asilomar Conf. on Signals, Systems and Computers, Nov 9-12, 2003.
2. V. G. Oklobdzija, D. Villeger, and S. S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach", IEEE Trans. on Computers, vol.45, no.3, March 1996.
3. Z. Huang and M. D. Ercegovac, "High-Performance Low-Power Left-to-Right Array Multiplier Design", IEEE Trans. on Computers, vol.54, no.3, March 2005.
4. K.-H. Chen, Y.-S. Chu, Y.-M. Chen, and J.-I. Guo, "A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique", ISCAS 2007: IEEE Intl. Symp. on Circuits and Systems, May 2007.
5. H. Zhu, Y. Zhu, C.-K. Cheng, and D. M. Harris, "An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization", ASP-DAC'07, Asia and South Pacific Design Automation Conference, Jan 23-26, 2007.
6. P.-M. Seidel, "Dynamic Operand Modification for Reduced Power Multiplication", 36th Asilomar Conf. on Signals, Systems and Computers, vol.1, Nov 2002.
7. K.-C. Kuo and C.-W. Chou, "Low Power Multiplier with Bypassing and Tree Structure", IEEE Asia Pacific Conf. on Circuits and Systems, APCCAS 2006, Dec 2006.
8. K. Chong, B.-H. Gwee, and J. S. Chang, "A Micropower Low-Voltage Multiplier With Reduced Spurious Switching", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol.13, no.2, Feb 2005.
9. V. G. Moshnyaga and K. Tamaru, "A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers", IEEE Intl. Symp. on Circuits and Systems, ISCAS '95, vol.3, May 1995.