Low power multiplier with bypassing and tree strucuture

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2006, Pages 602-605

  Kuo, Ko Chi ^a   Chou, Chi Wen ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

Bypassing method; Low power; Multiplier; Tree structure

Indexed keywords

FREQUENCY MULTIPLYING CIRCUITS; NETWORKS (CIRCUITS); STANDARDS; TREES (MATHEMATICS);

ASIA-PACIFIC; BYPASSING METHOD; CRITICAL PATHS; LOW POWER; LOW POWERS; MULTIPLIER; MULTIPLIER DESIGN; NEW DESIGN; POWER SAVINGS; POWER-DELAY PRODUCTS; SIMULATION RESULTS; SWITCHING ACTIVITIES; TREE STRUCTURE; TREE STRUCTURES;

ENERGY CONSERVATION;

EID: 50249162589     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2006.342060     Document Type: Conference Paper

References (6)

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