Optimized synthesis of sum-of-products

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2003, Pages 867-872

  Zimmermann, Reto ^a   Tran, David Q ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL-BASED DESIGNS; DATAPATH GENERATORS; DATAPATH LIBRARY CELLS; PARTIAL PRODUCTS; SUM-OF-PRODUCT (SOP) BLOCKS;

ADDERS; ALGORITHMS; ARRAYS; BINARY CODES; COMPUTER HARDWARE; DIGITAL LIBRARIES; FREQUENCY MULTIPLYING CIRCUITS; NETWORKS (CIRCUITS); OPTIMIZATION;

DATABASE SYSTEMS;

EID: 4143057885     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. I. Koren, Computer Arithmetic Algorithms, Prentice Hall, 1993.
2. B. Parhami, Computer Arithmetic: Algorithms and Hardware, Oxford University Press, 2000.
3. M. D. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers, 2004.
4. C. N. Lyu and D. W. Matula, "Redundant Binary Booth Receding," Proc. 12th Symp. Computer Arithmetic, July 1995, pp. 50-57.
5. Y. Dumonteix and H. Mehrez, "A Family of Redundant Multipliers Dedicated to Fast Computation for Signal Processing." Proc. IEEE Int. Symp. Circuits and Systems, May 2000, pp. 325-328.
6. V. G. Oklobdzija, D. Villeger, and S. S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach," IEEE Trans. Computers, vol. 45, no. 3, pp. 294-305, March 1996.
7. R. Zimmermann, Binary Adder Architectures for Cell-Based VLSI and their Synthesis, Ph.D. thesis, Swiss Federal Institute of Technology (ETH) Zurich, Hartung-Gorre Verlag, 1998.
8. R. E. Ladner and M. J. Fischer, "Parallel Prefix Computation," J. ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.
9. A. Tyagi, "A Reduced-Area Scheme for Carry-Select Adders," IEEE Trans. Computers, vol. 42, no. 10, pp. 1162-1170, Oct 1993.
10. R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. Computers, vol. 31, no, 3, pp. 260-264, Mar 1982.
11. J. Sklansky, "Conditional Sum Addition Logic," IRE Trans. Electronic Computing, vol. EC-9, no. 6, pp. 226-231, Jun 1960.
12. P. M. Kogge and H. S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans. Computers, vol. 22, no. 8, pp. 786-793, Aug 1973.
13. R. Zimmermarm, "Non-Heuristic Optimization and Synthesis of Parallel-Prefix Adders," Proc. Int. Workshop on Logic and Architecture Synthesis, Dec 1996, pp. 123-132.
14. J. P. Fishburn, "A Depth-Decreasing Heuristic for Combinational Logic; or How to Convert a Ripple-Carry Adder into a Carry-Lookahead Adder or Anything In-Between," Proc. 27th Design Automation Conference, 1990, pp. 361-364.