A high-speed/low-power multiplier using an advanced spurious power suppression technique

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3139-3142

  Chen, Kuan Hung ^a   Chu, Yuan Sun ^a   Chen, Yu Min ^a   Guo, Jiun In ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; LOGIC GATES; SIGNAL FILTERING AND PREDICTION; SPURIOUS SIGNAL NOISE; SWITCHING NETWORKS;

DATA TRANSITION; POWER REDUCTION; SPURIOUS POWER SUPPRESSION TECHNIQUE (SPST);

MULTIPLYING CIRCUITS;

EID: 34548851980     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378096     Document Type: Conference Paper

References (12)

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