Dynamic operand modification for reduced power multiplication

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2002, Pages 52-56

  Seidel, Peter Michael ^a  

^a Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; ENERGY UTILIZATION; OPTIMIZATION;

BINARY MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0037967630     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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10. P.-M. Seidel, Lee McFearin, and David W. Matula. Binary multiplication radix-32 and radix-256. In Proceedings of the 15th IEEE International Symposium on Computer Arithmetic (Arith15), pages 23-32, 2001.
11. C.S. Wallace. A suggestion for parallel multipliers. IEEE Trans. Electron. Comput., EC-13:14-17, 1964.
12. K.E. Wires, M.J. Schulte, and J.E. Stine. Combined IEEE compliant and truncated floating point multipliers for reduced power dissipation. In Proceedings of the IEEE International Conference on Computer Design 2001, pages 497-500, 2001.