Accurate timing analysis using SAT and pattern-dependent delay models

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1018-1023

  Tadesse, D ^a   Sheffield, D ^a   Lenge, E ^c   Bahar, R I ^a   Grodsteint, J ^b  

^a BROWN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; DECISION THEORY; MATHEMATICAL MODELS; PROBLEM SOLVING; SILICON COMPOUNDS;

ACCURATE TIMING ANALYSIS; DECISION PROBLEMS; PATTERN-DEPENDENT DELAY MODELS; SAT;

DELAY CIRCUITS;

EID: 34548301422     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364427     Document Type: Conference Paper

References (22)

1. S. Pilarski A. Pierzynska. Pitfalls in delay fault testing. IEEE Transactions on CAD, 16(3):321-329, Mar. 2002.
2. F. Aloul, S. Hassoun, K. Sakallah, and D. Blaauw. Robust sat-based search algorithm for leakage power reduction. In PATMOS '02, pages 167-177, 2002.
3. A. Biere, A. Cimatti, E. Clarke, O. Strichman, and Y. Zhu. Advances in Computer Science, volume 58, chapter Bounded Model Checking. Academic Press, 2003.
4. A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu. Symbolic model checking using SAT procedures instead of BDDs. In ACM/IEEE Conference on Design automation, pages 317-320, 1999.
5. D. Blaauw, V. Zolotov, S. Sundareswaran, C. Oh, and R. Panda. Slope propagation in static timing analysis. In ICCAD, Nov. 2000.
6. P. Chen and K. Keutzer. Towards true crosstalk noise analysis. In ICCAD, pages 132-138, 1999.
7. P. Chen, D. Kirkpatrick, and K. Keutzer. Switching window computation for static timing analysis in presence of crosstalk noise. In ICCAD, pages 331-337, Nov. 2000.
8. S. Devadas, K. Keutzer, S. Malik, and A. Wang. Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Transactions on CAD, 12(12):1924-1936, December 1993.
9. A. Gattiker, S. Nassif, R. Dinakar, and C. Long. Timing yield estimation from static timing analysis. In International Symposium on Quality Electronic Design, page 437, 2001.
10. J. Grodstein, D. Bhavsar, V. Bettada, and R. Davies. Automatic generation of critical-path tests for a partial-scan microprocessor. In ICCD '03, page 180, 2003.
11. A. Krstic, J. Liou, Y. Jiang, and K. Cheng. Delay testing considering crosstalk-induced effects. In IEEE International Test Conference, page 558, 2001.
12. T. Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on CAD, 11(1), January 1992.
13. L. Lee, L. Wang, T. Mak, and K. Cheng. A path-based methodology for post-silicon timing validation. In ICCAD, pages 713- 720, Nov. 2004.
14. Y Mahajan, Z. Fu, and S. Malik. Zchaff2004: An efficient sat solver. Lecture Notes in Computer Science, 3542:360-375, 2005.
15. P. Maurer. Two new techniques for unit-delay compiled simulation. IEEE Transactions on CAD, 11(9):1120-1130, Sept. 1992.
16. K. Nepal, H. Song, R. Bahar, and J. Grodstein. Resta: a robust and extendable symbolic timing analysis tool. In GLSVLSI, pages 407-412, 2004.
17. S.Devadas, K. Keutzer, S. Malik, and A. Wang. Certified timing verification and the transition delay of a logic circuit. IEEE Transactions on VLSI Systems, 2(3):1063-8210, September 1994.
18. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli. Sequential circuit design using synthesis and optimization. In ICCD, Oct. 1992.
19. J. Silva and K. Sakallah. Dynamic search-space pruning techniques in path sensitization. In DAC, pages 705-711, 1994.
20. J. Silva and K. Sakallah. Efficient and robust test generation-based timing analysis. In ISCAS, pages 660-663, Aug. 2003.
21. L. Silva, J. Silva, L. Silveira, and K. Sakallah. Satisfiability models and algorithms for circuit delay computation. ACM Trans. on Design Automation of Electronic Systems (TODAES), 7(1):137-158, 2002.
22. S. Sun, D. Du, and H. Chen. Efficient timing analysis for CMOS circuits considering data dependent delays. In ICCS '94, pages 156-159, 1994.