Memory-efficiency and high-speed architectures for forward and inverse DCT with multiplierless operation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4319 LNCS, Issue , 2006, Pages 802-811

  Sung, Tze Yun ^a   Sun, Mao Jen ^a   Shieh, Yaw Shih ^a   Hsin, Hsi Chin ^b  

^a CHUNG HUA UNIVERSITY   (Taiwan)

^b NATIONAL FORMOSA UNIVERSITY   (Taiwan)

Author keywords

DCT; High performances; IDCT; Memory efficiency; Parallel pipelined architecture

Indexed keywords

EFFICIENCY; IMAGE PROCESSING; INVERSE TRANSFORMS; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES; PIPELINE PROCESSING SYSTEMS; PIPELINES; STATIC RANDOM ACCESS STORAGE;

HIGH-PERFORMANCES; HIGH-SPEED ARCHITECTURES; IDCT; IMAGE PROCESSING SYSTEM; INVERSE DISCRETE COSINE TRANSFORMS; MEMORY EFFICIENCY; PARALLEL PIPELINED ARCHITECTURES; TWO DIMENSIONAL DISCRETE COSINE TRANSFORM;

DISCRETE COSINE TRANSFORMS;

EID: 70350276484     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11949534_80     Document Type: Conference Paper

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