New Cost-Effective VLSI Implementation of a 2-D Discrete Cosine Transform and Its Inverse

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 14, Issue 4, 2004, Pages 405-415

  Gong, Danian ^a,b   He, Yun ^b   Cao, Zhigang ^b  

^a ESS Technology   (United States)

^b TSINGHUA UNIVERSITY   (China)

Author keywords

Discrete cosine transform (DCT); Row column decomposition; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COSINE TRANSFORMS; IMAGE CODING; INTERCONNECTION NETWORKS; MATRIX ALGEBRA; MULTIPLEXING; REAL TIME SYSTEMS; VIDEO SIGNAL PROCESSING; VLSI CIRCUITS;

ACCURACY TESTING SYSTEM; DISCRETE COSINE TRANSFORM (DCT); REAL-TIME COMPUTING; ROW COLUMN DECOMPOSITION;

SIGNAL PROCESSING;

EID: 2042436420     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2004.825575     Document Type: Review

References (28)

1. Digital Compression and Coding of Continuous-Tone Still Images, Feb. 1992. ISO/IEC DIS 10918-1.
2. Video Codec for Audio-Visual Services at p × 64 kbit/s, 1993.
3. Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to About 1.5 Mbit/s, Nov. 1991. ISO CD 11172.
4. Generic Coding of Moving Pictures and Associated Audio Information: Video, Nov. 1994. ISO/ICE 13 818-2.
5. ITU-T Recommendation H.263. Video Coding for Low Bit-Rate Communication, 1996.
6. ITU-T Recommendation H.263+, Jan. 27, 1999. Draft 21.
7. MPEG-4 Video Verification Model Version 14. 0, Oct. 1999.
8. M. Sun et al., "VLSI implementation of a 16 × 16 discrete cosine transform," IEEE Trans. Circuits and Syst., vol. 36, pp. 610-617, Apr. 1989.
9. N. I. Cho and S. U. Lee, "Fast algorithm and implementation of 2-D discrete cosine transform," IEEE Trans. Circuits Syst., vol. 38, pp. 297-305, Mar. 1991.
10. J. F. Yang, B. L. Bai, and S. H. Hsia, "An efficient two-dimensional inverse discrete cosine transform algorithm for HDTV receivers," IEEE Trans. Circuits Syst. Video Technol., vol. 5, pp. 25-30, Oct. 1995.
11. C. Loeffler, A. Ligtenberg, and G. S. Moschytz, "Practical fast 1-D DCT algorithms with 11 multiplications," in Proc. IEEE ICASSP, vol. 2, Feb, 1989, pp. 988-991.
12. U. Totzek, F. Matthiesen, S. Wohlleben, and T. G. Noll, "CMOS VLSI implementation of the 2D-DCT with linear processor arrays," in Proc. IEEE ICASSP, vol. 2, 1990, pp. 937-940.
13. S.-I. Uramoto et al., "A 100-MHz 2-D discrete cosine transform core processor," IEEE J. Solid-State Circuits, vol. 27, pp. 492-499, Apr. 1992.
14. W. Li, "DCT-IDCT processor design for high data rate image coding," IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp. 135-146, June 1992.
15. P. A. Ruetz, P. Tong, D. Bailey, P. A. Luthi, and P. H. Ang, "A high-performance full-motion video compression chip set," IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp. 111-122, June 1992.
16. P. A. Ruetz and P. Tong, "A 160 M pixels IDCT processor for HDTV," IEEE Micro, vol. 12, pp. 28-32, Oct. 1992.
17. C. M. Wu and A. Chiou, "A SIMD-systolic architecture and VLSI chip for the two-dimensional DCT and IDCT," IEEE Trans. Consumer Electron., vol. 39, pp. 859-869, Nov. 1993.
18. A. Matisetti and A. N. Willson Jr., "A 100 MHz 2-D 8 DCT-IDCT processor for HDTV applications," IEEE Trans. Circuits Syst. Video Technol., vol. 5, pp. 158-165, Apr. 1995.
19. T. Masaki et al., "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding," IEEE Trans. Circuits Syst. Video Technol., vol. 5, pp. 387-395, Oct. 1995.
20. Y. T. Chang and C. L. Wang, "New systolic array implementation of the 2-D discrete cosine transform and its inverse," IEEE Trans. Circuits Syst. Video Technol., vol. 5, pp. 150-157, Apr. 1995.
21. K. Kim, S. H. Jang, and S. H. Kwon, "An improvement of VLSI architecture for 2-dimensional discrete cosine transform and its inverse," in Proc. Visual Communications and Image Processing, vol. 2727, Orlando, FL, Mar. 1996, pp. 1017-1027.
22. R. Sarmiento et al., "A 600 MHz 2D-DCT processor for MPEG applications," in Proc. Conference Record of the Thirty-First Asilomar Conf., vol. 2, 1998, pp. 1527-1531. 1997.
23. K. Kim and J. S. Koh, "An area efficient DCT architecture for MPEG-2 video encoder," IEEE Trans. Consumer Electron., vol. 45, pp. 62-67, Feb. 1999.
24. K.-H. Cheng, C.-S. Huang, and C.-P. Lin, "The design and implementation of DCT/IDCT Chip," in Proc. IEEE-ISCAS, Geneva, Switzerland, May 2000, pp. 741-745.
25. Y. He and D. Gong, "A Programmable and Parallel Video Signal Processor for Hybrid Video Coding," Chinese Patent 01102228.0, Jan. 2001.
26. T. S. Chang, C. S. Kung, and C. W. Jen, "A simple processor core design for DCT/IDCT," IEEE Trans. Circuits Syst. Video Technol., vol. 10, pp. 439-447, Apr. 2000.
27. Y. P. Lee, T. H. Chen, L. G. Chen, M. J. Chen, and C. W. Ku, "A cost-effective architecture for 8 × 8 two-dimensional DCT/IDCT using direct method," IEEE Trans. Circuits Syst. Video Technol., vol. 7, pp. 459-467, June 1997.
28. T. Xanthopoulos and A. P. Chandrakasan, "A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity," IEEE J. Solid-State Circuits, vol. 34, pp. 693-703, May 1999.