New matrix formulation for two-dimensional DCT/IDCT computation and its distributed-memory VLSI implementation

IEE Proceedings: Vision, Image and Signal Processing

Volumn 149, Issue 2, 2002, Pages 97-107

  Hsiao, S F ^a   Tseng, J M ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COSINE TRANSFORMS; MATRIX ALGEBRA; VLSI CIRCUITS;

DISTRIBUTED MEMORY STRUCTURES;

IMAGE COMPRESSION;

EID: 0036544024     PISSN: 1350245X     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-vis:20020241     Document Type: Conference Paper

References (10)

1. VLSI implementation of a 16 × 16 discrete cosine transform
2. A 100-MHz 2-D discrete cosine transform core processor
3. A 100 MHz 2-D 8 × 8 DCT/IDCT processor for HDTV applications
4. DCT/IDCT processor design for high data rate image coding
5. A refined fast 2-D discrete cosine transform algorithm
6. A cost-effective architecture for 8 × 8 two-dimensional DCT/IDCT using direct method
7. Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log N
8. A high-throughput, low-power architecture and its VLSI implementation for DFT/IDFT computation
9. High-throughput VLSI architectures for the 1-D and 2-D discrete cosine transform
10. A new fast DCT algorithm and its systolic VLSI implementation