A cost-effective 8x8 2-d idct core processor with folded architecture

IEEE Transactions on Consumer Electronics

Volumn 45, Issue 2, 1999, Pages 333-339

  Chen, Thou Ho ^a  

^a SOUTHERN TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COSINE TRANSFORMS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE STRUCTURES; VLSI CIRCUITS;

DOUBLE METAL TECHNOLOGY; INVERSE DISCRETE COSINE TRANSFORM (IDCT);

CONSUMER ELECTRONICS;

EID: 0032653934     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.793417     Document Type: Article

References (23)

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