A 35 /spl mu/W 1.1 v gate array 8/spl times/8 IDCT processor for video-telephony

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 1998, Pages 2993-2996

  Rambaldi, Roberto ^a   Ugazzoni, Alessnizdro ^a   Guerrieri, Roberto ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DESIGN TECHNIQUE; FAST ALGORITHMS; IMAGE SEQUENCE; MAXIMUM THROUGH-PUT; PORTABLE APPLICATIONS; PORTABLE VIDEO; SIGNAL CORRELATION;

CMOS INTEGRATED CIRCUITS; SIGNAL PROCESSING;

INVERSE TRANSFORMS;

EID: 0031636938     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1998.678155     Document Type: Conference Paper

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