Defragmentation algorithms for partially reconfigurable hardware

IFIP International Federation for Information Processing

Volumn 240, Issue , 2007, Pages 41-53

  Koester, Markus ^a   Kalte, Heiko ^b   Porrmann, Mario ^a   Rückert, Ulrich ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

^b UNIVERSITY OF WESTERN AUSTRALIA   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; DYNAMIC MODELS; DYNAMICS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; MICROELECTRONICS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; COMPUTER SIMULATION;

DYNAMIC RE-CONFIGURATION; DYNAMICALLY RECONFIGURABLE SYSTEMS; MICROELECTRONIC SYSTEMS; PARTIAL DYNAMIC RECONFIGURATION; REALISTIC SIMULATION; RECONFIGURABLE SYSTEMS; RESOURCE MANAGEMENT; RESOURCE-EFFICIENT; DEVICE UTILIZATION;

RECONFIGURABLE HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548776548     PISSN: 15715736     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-0-387-73661-7_4     Document Type: Conference Paper

References (11)

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