Cross-architectural design space exploration tool for reconfigurable processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 958-963

  Bauer, Lars ^a   Shafique, Muhammad ^a   Henkel, Jörg ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; ECONOMIC AND SOCIAL EFFECTS; GENERAL PURPOSE COMPUTERS; SYSTEMS ANALYSIS;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR; ARCHITECTURAL DECISION; ARCHITECTURAL PARAMETERS; DESIGN SPACE EXPLORATION; DESIGN-SPACE EXPLORATION TOOL; GENERAL PURPOSE PROCESSORS; RECONFIGURABLE FABRICS; RECONFIGURABLE PROCESSORS;

INTEGRATED CIRCUIT DESIGN;

EID: 70350043890     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090803     Document Type: Conference Paper

References (17)

1. S. Vassiliadis, D. Soudris, "Fine- and Coarse-Grain Reconfigurable Computing", Springer, ISBN 978-1-4020-6504-0, 2007.
2. C. Bobda, "Introduction to Reconfigurable Computing", Springer, ISBN 978-1-4020-6088-5, 2007.
3. J. Henkel, "Closing the SoC Design Gap", IEEE Computer, vol. 36, issue 9, pp. 119-121, 2003.
4. Z. Li, S. Hauck, "Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation", Int'l Symp. on FPGAs, pp. 187-195, 2002.
5. F. Bouwens, et al., "Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array", ARC, pp. 1-13, 2007.
6. M. Ullmann, et al., "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration", Int'l Parallel and Distributed Processing Symposium (IPDPS), pp. 135-142, 2004.
7. M. Majer, J. Teich, A. Ahmadinia, C. Bobda, "The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer", VLSI Signal Processing Systems, pp. 15-31, 2007.
8. E. Lübbers, M. Platzner, "ReconOS: An RTOS supporting Hard-and Software Threads", FPL, pp. 441-446, 2007.
9. P. Lysaght, B. Blodget, J. Mason, J. Young, B. Bridgeford, "Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration on Xilinx FPGAs", FPL, pp. 1-6, 2006.
10. S. Sawitzki, A. Gratz, R. G. Spallek, "CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism", Conf. on Parallel and RT Systems, pp. 213-224, 1998.
11. Z. A. Ye et al., "CHIMAERA: a High Performance Architecture with a tightly coupled reconfigurable functional unit", Intl. Symp. on Computer Architecture (ISCA), pp. 225-235, 2000.
12. S. Vassiliadis, et al., "The MOLEN polymorphic processor", Trans. on Computers, vol. 53, issue 11, pp. 1363-1375, 2004.
13. L. Bauer, M. Shafique, S. Kramer, J. Henkel, "RISPP: Rotating Instruction Set Processing Platform", Design Automation Conference (DAC), pp. 791-796, 2007.
14. L. Bauer, M. Shafique, S. Kreutz, J. Henkel, "Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set", Conf. on Design, Automation & Test (DATE), pp. 752-757, 2008.
15. L. Bauer, M. Shafique, J. Henkel, "A Computation- and Communication-Infrastructure for Modular Special Instructions in a Dynamically Reconfigurable Processor", FPL, pp. 203-208, 2008.
16. MiBench (http://www.eecs.umich.edu/mibench/).
17. C. Lee, M. Potkonjak, W. H. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems", MICRO, pp. 330-335, 1997.