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Volumn , Issue , 2009, Pages 1200-1206

Evaluation of a module based memory system with an LCP flex interconnect

Author keywords

[No Author keywords available]

Indexed keywords

BOTTOM LAYERS; CSP PACKAGES; DATA RATES; DIFFERENTIAL PAIRS; GRID ARRAYS; MEMORY CONTROLLER; MEMORY MODULES; MEMORY SYSTEMS; MEMORY TESTS; MODULE-BASED; SOLDER BALLS; SYSTEM MARGIN; THROUGH HOLE;

EID: 70349682159     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074164     Document Type: Conference Paper
Times cited : (5)

References (20)
  • 1
    • 51349165885 scopus 로고    scopus 로고
    • Computing trends and applications driving memory performance
    • Tokyo, Japan, November 28
    • Steven Woo, " Computing Trends And Applications Driving Memory Performance, " Rambus Developer Forum, Tokyo, Japan, November 28, 2007.
    • (2007) Rambus Developer Forum
    • Woo, S.1
  • 2
    • 63449097179 scopus 로고    scopus 로고
    • A 16GB/s/link, 64GB/s bidirectional asymmetric memory interface
    • Honolulu, HI, June
    • K. Chang, et al., " A 16Gb/s/link, 64GB/s Bidirectional Asymmetric Memory Interface, " Symposium on VLSI Circuist, Honolulu, HI, June 2008.
    • (2008) Symposium on VLSI Circuist
    • Chang, K.1
  • 3
    • 51949089239 scopus 로고    scopus 로고
    • A 16-GB/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process
    • Honolulu, HI, June
    • N. Nguyen, et al., " A 16-Gb/s Differential I/O Cell with 380fs RJ in an Emulated 40nm DRAM Process", Symposium on VLSI Circuist, Honolulu, HI, June 2008.
    • (2008) Symposium on VLSI Circuist
    • Nguyen, N.1
  • 4
    • 67349120647 scopus 로고    scopus 로고
    • A 16GB/s 65 nm CMOS transceiver for a memory interface
    • Fukuoka, Japan, November 3-5
    • J. Chun, et al., " A 16Gb/s 65 nm CMOS Transceiver for a Memory Interface, " IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, November 3-5, 2008.
    • (2008) IEEE Asian Solid-State Circuits Conference
    • Chun, J.1
  • 5
    • 57849129407 scopus 로고    scopus 로고
    • Clocking circuits for a 16GB/s memory interface
    • San Jose, CA, September
    • T. Wu, et al., " Clocking Circuits for a 16Gb/s Memory Interface, " IEEE Custom Integrated Circuits Conference, San Jose, CA, September 2008.
    • (2008) IEEE Custom Integrated Circuits Conference
    • Wu, T.1
  • 7
    • 84866420397 scopus 로고    scopus 로고
    • The design and signal integrity analysis of a TB/sec memory system
    • CA, February
    • W. T. Beyene, et al. " The Design and Signal Integrity Analysis of a TB/sec Memory System, " DesignCon, Santa Clara, CA, February 2009.
    • (2009) DesignCon, Santa Clara
    • Beyene, W.T.1
  • 8
    • 70349672005 scopus 로고    scopus 로고
    • Designing scalable 10G backplane interconnect systems utilizing advanced verification methodologies
    • Santa Clara, CA
    • K.Grundy et al. " Designing Scalable 10G Backplane Interconnect Systems Utilizing Advanced Verification Methodologies, " 8-WP2, DesignCon2006, Santa Clara, CA.
    • 8-WP2, DesignCon2006
    • Grundy, K.1
  • 9
    • 33845567938 scopus 로고    scopus 로고
    • Flex-circuit chip-to-chip interconnects
    • San Diego, CA, May 30-Jun. 2
    • H. Braunisch et al, " Flex-circuit chip-to-chip interconnects, " Proc. IEEE Electronic Compon. Technol. Conf. (ECTC), San Diego, CA, May 30-Jun. 2, 2006, pp. 1853-1859.
    • (2006) Proc. IEEE Electronic Compon. Technol. Conf. (ECTC) , pp. 1853-1859
    • Braunisch, H.1
  • 10
    • 40549112357 scopus 로고    scopus 로고
    • High-speed flex circuit chip-to- Chip interconnects
    • H. Braunisch et al, " High-Speed Flex Circuit Chip-to- Chip Interconnects, " IEEE Trans. On Advanced Packaging, vol. 31, No. 1 (2008), pp. 82-90.
    • (2008) IEEE Trans. on Advanced Packaging , vol.31 , Issue.1 , pp. 82-90
    • Braunisch, H.1
  • 15
    • 0242695808 scopus 로고    scopus 로고
    • An accurate and efficient analysis method for multi-GB/s chip-to-chip signaling schemes
    • June
    • B.K. Casper et al., " An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes, " IEEE Symposium on VLSI Circuits, June 2002, pp. 54-57.
    • (2002) IEEE Symposium on VLSI Circuits , pp. 54-57
    • Casper, B.K.1
  • 16
    • 32944464824 scopus 로고    scopus 로고
    • Performance specification of interconnect
    • February 2003
    • B. Ahmad, " Performance Specification of interconnect", DesignCon, February 2003.
    • DesignCon
    • Ahmad, B.1
  • 18
    • 34748897001 scopus 로고    scopus 로고
    • Channel compliance testing utilizing novel statistical eye methodology
    • February
    • A. Sanders, M. Resso, and J. D'Ambrosia, " Channel compliance testing utilizing novel statistical eye methodology, " DesignCon, February 2004.
    • (2004) DesignCon
    • Sanders, A.1    Resso, M.2    D'ambrosia, J.3
  • 19
    • 0003554146 scopus 로고    scopus 로고
    • The MathWorks Inc. Natick, MA
    • MATLAB User's Guide, The MathWorks Inc., Natick, MA 2000.
    • (2000) MATLAB User's Guide
  • 20
    • 28144452073 scopus 로고    scopus 로고
    • Agilent Technologies, February, Agilent Technologies, Santa Rosa, CA
    • Agilent Advanced Design System User's Guide, Agilent Technologies, February 2001, Agilent Technologies, Santa Rosa, CA.
    • (2001) Agilent Advanced Design System User's Guide


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.