The design and signal integrity analysis of a TB/sec memory system

Designcon 2009

Volumn 1, Issue , 2009, Pages 533-554

  Beyene, Wendem T ^a   Madden, Chris ^a   Kim, Namhoon ^a   Lee, Haechang ^a   Frans, Yohan ^a   Leibowitz, Brian ^a   Chun, Jung Hoon ^a   Aleksic, Marko ^a   Chang, Ken ^a   Vaidyanath, Arun ^a   Seeker, Dave ^a   Li, Ming ^a   Perego, Rich ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BI-DIRECTIONAL; DESIGN AND ANALYSIS; DIFFERENTIAL SIGNALING; HIGH-SPEED MEMORY; INTERCONNECT TECHNOLOGY; INTERFACE TECHNOLOGY; LOW SWING; MEMORY SYSTEMS; PROTOTYPE SYSTEM; SIGNAL INTEGRITY ANALYSIS; SYSTEM LEVELS; VOLTAGE MARGIN;

DATA TRANSFER RATES; DESIGN; MEMORY ARCHITECTURE; TIMING CIRCUITS;

COST BENEFIT ANALYSIS;

EID: 84866420397     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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