Fine-grained self-healing hardware for large-scale autonomic systems

Proceedings - International Workshop on Database and Expert Systems Applications, DEXA

Volumn 2003-January, Issue , 2003, Pages 707-712

  Kumar, V V ^a   Lach, J ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

Circuit faults; Costs; Electrical fault detection; Hardware; Integrated circuit reliability; Large scale systems; Reconfigurable logic; Redundancy; Software systems; Table lookup

Indexed keywords

COMPUTER HARDWARE; COST REDUCTION; COSTS; ELECTRIC FAULT LOCATION; EXPERT SYSTEMS; FAULT DETECTION; HARDWARE; LARGE SCALE SYSTEMS; LOGIC CIRCUITS; RECONFIGURABLE HARDWARE; RECOVERY; SOFTWARE RELIABILITY; TABLE LOOKUP;

CIRCUIT FAULTS; ELECTRICAL FAULT DETECTIONS; INTEGRATED CIRCUIT RELIABILITY; RECONFIGURABLE LOGIC; SOFTWARE SYSTEMS;

REDUNDANCY;

EID: 70349583362     PISSN: 15294188     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DEXA.2003.1232104     Document Type: Conference Paper

References (16)

1. Abramovici, M., et al., "Using RovingSTARs for online testing and diagnosis of FPGAs in fault-tolerant applications," International Test Conference, 973-82, 1999
2. Abramovici, M., Stroud, C., "BIST-based delay-fault testing in FPGAs," On-Line Testing Workshop, 131-4, 2002
3. Cong, J., Li, Z., Bagrodia, R., "Acyclic multi-way partitioning of boolean networks," Design Automation Conference, 670-5, 1994
4. Corno, F., Sonza Reorda, M., Squillero, G., ITC '99 Benchmarks, http://www.cad.polito.it/tools/itc99.html
5. Doumar, A., Kaneko, S., Ito, H., "Defect and fault tolerance FPGAs by shifting the configuration data," International Symposium on Defect and Fault Tolerance in VLSI Systems, 377-85, 1999
6. Emmert, J., et al., "Dynamic fault tolerance in FPGAs via partial reconfiguration," IEEE Symposium on Field-Programmable Custom Computing Machines, 165-74, 2000
7. Ganek, A.G., Corbi, T.A., "The dawning of the autonomic computing era," IBM Systems Journal, vol. 42, no. 1, 5-17, January 2003
8. Gupta, S., Pradhan, D., "Utilization of on-line (concurrent) checkers during built-in self-test and vice versa," IEEE Transactions on Computers, vol. 45, 63-73, January 1996
9. Jann, J., Browning, L.M., Burugula, R.S., "Dynamic reconfiguration: Basic building blocks for autonomic computing on IBM pSeries servers," IBM Systems Journal, vol. 42, no. 1, 29-37, January 2003
10. Jha, N.K., Wang, S.J., "Design and synthesis of self-checking VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 12, 879-87, June 1993
11. Karri, R., Mukherjee, N., "Versatile BIST: An integrated approach to on-line/off-line BIST," International Test Conference, 910-7, 1998
12. Lach, J., Mangione-Smith, W.H., Potkonjak, M., "Enhanced FPGA reliability through efficient run-time fault reconfiguration," IEEE Transactions on Reliability, vol. 49, no. 3, 296-304, September 2000
13. Leveugle, R., Saucier, G., "Optimized synthesis of concurrently checked controllers," IEEE Transactions on Computers, vol. 39, 419-25, April 1990
14. Saluja, K.K., Sharma, R., Kime, C.R., "A concurrent testing technique for digital circuits," IEEE Transactions on Computer-Aided Design, vol. 7, no. 12, 1250-60, December 1988
15. Singh, R., Knight, J., "Concurrent testing in high-level synthesis," International Symposium on High-Level Synthesis, 96-103, 1994
16. Tarnick, S., "Controllable self-checking checkers for conditional concurrent checking," IEEE Transactions on Computer-Aided Design, vol. 14, 547-53, May 1995