Defect and fault tolerance FPGAs by shifting the configuration data

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 377-385

  Doumar, Abderrahim ^a   Kaneko, Satoshi ^a   Ito, Hideo ^a  

^a CHIBA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANT COMPUTER SYSTEMS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PROBABILITY;

CONFIGURABLE LOGIC BLOCKS (CLB);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033337090     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)