Tradeoffs in designing accelerator architectures for visual computing

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 164-175

  Mahesri, Aqeel ^a   Johnson, Daniel ^a   Crago, Neal ^a   Patel, Sanjay J ^a  

^a United States of America   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR ARCHITECTURES; AREA RATIOS; BENCHMARK SUITES; CACHE BANDWIDTH; DATA-COMMUNICATION; DESIGN SPACES; GENERAL PURPOSE; GRAPHICS RENDERING; HIGH THROUGHPUT; MEMORY HIERARCHY; MIMD ARCHITECTURE; MULTI-THREADING; PERFORMANCE TRADE-OFF; POOR PERFORMANCE; UNIPROCESSOR; VIDEO ENCODING; VISUAL COMPUTING;

BENCHMARKING; CACHE MEMORY; COMPUTER VISION; MULTITASKING;

ARCHITECTURAL DESIGN;

EID: 66749170578     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771788     Document Type: Conference Paper

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