Mapping control intensive kernels onto coarse-grained array architecture

2008 International SoC Design Conference, ISOCC 2008

Volumn 1, Issue , 2008, Pages

  Chang, Kyungwook ^a   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

Author keywords

Coarse grained reconfigurable array architecture; Control intensive kernel; Deblocking filter; Speculative execution

Indexed keywords

ARRAY ARCHITECTURE; COARSE-GRAINED; COARSE-GRAINED RECONFIGURABLE ARRAY ARCHITECTURE; DEBLOCKING FILTER; DEBLOCKING FILTERS; EMBEDDED APPLICATION; MACRO BLOCK; RECONFIGURABLE ARRAY; SIMULATION RESULT; SOFTWARE IMPLEMENTATION; SPECULATIVE EXECUTION;

COMPUTER SOFTWARE; IMAGE QUALITY; PROGRAMMABLE LOGIC CONTROLLERS;

ELECTRIC FILTERS;

EID: 69949084271     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCDC.2008.4815647     Document Type: Conference Paper

References (9)

1. R. Hartenstein, "A decade of reconfigurable computing: a visionary retrospective," in Proc. of Design Automation and Test in Europe Conf., pp. 642-649, March 2005.
2. H. Singh, M. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh, "MorphoSys: an integrated reconfigurable system for data-parallel and computationintensive applications," in IEEE Trans. On Computers, vol.49, no. 5, pp 465-481, May 2000. (Pubitemid 30897141)
3. B. Mei, S. Vernalde, D. Verkest, H. D. Man, R. Lauwereins, "ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfiguralbe matrix," in Proc of Field Programmable Logic And Applications, pp 166-173, December 2002.
4. R. Hartenstein, M. Herz, T.Hoffmann, U. Nageldinger, "KressArray Xplorer: a new CAD environment to optimize reconfiguralbe datapath array architectures," in Proc. of Asia and South Pacific Design Automation Conference, pp. 163-168, January 2000.
5. C. Albelo, et al., "Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter." in Proc. of Design Automation and Test in Europe Conf., pp. 1-6, April 2007.
6. J. Lee, Y. Kim, J. Jung, S. Kang, K. Choi, "Reconfigurable ALU Array Architecture with Conditional Execution", in Proc. of International SoC Design Conference, pp. 222-226, October 2004.
7. Y. Kim, M. Kiemb, C. Park, J. Jung, K. Choi, "Resource sharing and pipelining in coarse-grained reconfigurable architecture for domainspecific optimization," in Proc. of Design Automation and Test in Europe Conf., pp. 12-17, March 2005. (Pubitemid 44234568)
8. Y. Kim, I. Park, K. Choi, Y. Paek, "Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture," in Proc. of International Symposium on Low Power Electronics and Design, pp. 310-315, October 2006. (Pubitemid 46609755)
9. M. Jo, V. K. Prasad Arava, H. Yang, K. Choi, "Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecutre," in Proc. of IEEE International SoC Conference, pp. 127-130, September 2007.