Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: The H.264/AVC deblocking filter

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 177-182

  Arbelo, C ^a   Kanstein, A ^b   Lopez S ^a   Lopez J F ^a   Berekovic, M ^c   Sarmiento, R ^a   Mignolet, J Y ^c  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

^b Freescale Semiconductors   (France)

^c IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMAL MAPPING; DIGITAL FILTERS; PROGRAMMABLE LOGIC CONTROLLERS; STANDARDIZATION; STORAGE ALLOCATION (COMPUTER);

COARSE-GRAIN RECONFIGURABLE ARCHITECTURE; MEMORY ACCESSES;

IMAGE CODING;

EID: 34548316222     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364587     Document Type: Conference Paper

References (12)

1. T. Wiegand (Ed.), "Draft ITU-T Recommendation H.264 and Draft ISO/EEC 14496-10 AVC," Joint Video Team of ISO/IEC/JTC1/SC29/WG11 & ITU-TSGl6/Q.6 Doc. JVT-G050, Pattaya, Thailand, March 2003.
2. ISO/EEC JTC1/SC29 CD 11544, "Coded Representation of Picture and Audio Information - Progressive Bi-Level Image Compression", Recommendation H.262 Nov., 1993.
3. MPEG-4 Part 2: Visual (IS 14496-2), Doc. N2502, Atlantic City, N.J., USA, October 1998.
4. "Video coding for Low Bit Rate Communication", ITU-T Recommendation H.263, July 1995.
5. B. Mei, A Coarse-Grained Reconfigurable Architecture Template and its Compilation Techniques, PhD Thesis IMEC, January 2005.
6. M. Berekovic, A. Kanstein, D. Desmet, A. Bartic, B. Mei and J.Y. Mignolet, "Mapping of Video Compression Algorithms on the ADRES Coarse-Grain Reconfigurable Array", Workshop on Multimedia and Stream Processors'05, Barcelona, November 12, 2005.
7. H. Huebert, B. Stabernack and H. Richter, "Tool-Aided Performance Analysis and Optimization of an H.264 Decoder for Embedded System", Consumer Electronics, 2004 IEEE International Symposium on Consumer Electronics, pp. 400-405, Sept. 1-3, 2004.
8. X. Quan, L. Jilin, W. Shijie, Z. Jiandong. "H.264/AVC Baseline Profile Decoder Optimizations on Independent Platform", International Conference on Wireless Communications, Networking and Mobile Computing, 2005, Volume 2, pp. 1253-1256, 23-26 Sept. 2005
9. P. P. Chang and S. A. Mahlke and W. Y. Chen and N. J. Warter and W. W. Hwu, "IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors", Proc. of the 18th International Symposium on Computer Architecture (ISCA), pp. 266-275, 1991.
10. Scott A. Mahlke, "Exploiting Instruction-Level Parallelism in the Presence of Conditional Branches", PhD thesis, University of Illinois, Urbana IL, September 1996
11. B. Mei, S. Vernalde, D. Verkest, H. De Man, R. Lauwereins, "Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling", Proc of DATE 2003, Munich, March, 2003
12. Available at: http://iphorne.hhi.de/suehring/tml/index.htm