A 10Gb/s CMOS adaptive equalizer for backplane applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Gondi, Srikanth ^a   Lee, Jri ^a   Takeuchi, Daishi ^b   Razavi, Behzad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Kawasaki Microelectronics   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 27844506704     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. E. Jaussi et al., "An 8Gb/s Source-Synchronous I/O link with Adaptive Receiver Equalization, Offset Cancellation and Clock Deskew," ISSCC Dig. Tech. Papers, pp. 246 - 247, Feb., 2004.
2. M. M. Green et al., "A BiCMOS 10Gb/s Adaptive Cable Equalizer," ISSCC Dig. Tech. Papers, pp. 482-483, Feb., 2004.
3. Y. Tomita et al., "A 10Gb/s Receiver with Equalizer and On-Chip ISI Monitor in 0.11μm CMOS," Symp. VLSI Circuits, pp. 202-205, June, 2004.
4. E. Sackinger, W. C. Fischer, "A3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 Receivers," IEEE J. Solid-State Circuits, vol. 35, pp. 1884-1888, Dec., 2000.
5. J.-S. Choi et al., "A 0.18μm CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method," IEEE J. Solid-State Circuits, pp. 419-425, March, 2004.