A 3.4 GB/S low latency 1 bit input digital FIR-filter in 0.13 μM CMOS

Proceedings of the 14th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2007

Volumn , Issue , 2007, Pages 181-184

  Fredriksson, H ^a   Svensson, C ^a   Alvandpour, A ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Carry save; CMOS; Equalizer; FIR; Gb IO

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; INTEGRATED CIRCUITS; STANDARDS; WAVE FILTERS;

CARRY-SAVE; CMOS; CMOS TECHNOLOGIES; EQUALIZER; FIR; GB-IO; HIGH SPEEDS; INTERNATIONAL CONFERENCES; LOW-LATENCY; MIXED SIGNALS; SIMULATION RESULTS;

DECISION FEEDBACK EQUALIZERS;

EID: 47749083524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MIXDES.2007.4286146     Document Type: Conference Paper

References (4)

1. Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic, Fred Chen, et. al., Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell IEEE Journal of solid-state circuits Vol. 38 No. 12, December 2003 pp. 2121-2130
2. Robert Payne, Paul Landman, Bhavesh Bhakta, Sridhar Ramaswamy, et. al., A 6.25Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels IEEE Journal of solid-state circuits vol. 40 No. 12 December 2005 pp. 2646-2657
3. M. Meghelli, S. Rylov, et. al., A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transciver in 90nm CMOS IEEE International Solid-State Circuits Conference, 2006 Digest of Technical Papers. pp.80-81
4. Tobias G. Noll, Carry-Save Architectures for High-Speed Digital Signal Processing Journal of VLSI Signal Processing, 3, 1991, pp. 121-140