A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 202-205

  Tomita, Yasumoto ^a   Kibune, Masaya ^b   Ogawa, Junji ^c   Walker, William W ^c   Tamura, Hirotaka ^b   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

^c FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

CDR; CMOS; Equalizer; ISI; Receiver

Indexed keywords

DATA ACQUISITION; DEMULTIPLEXING; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER UTILIZATION; EQUALIZERS; MICROPROCESSOR CHIPS; SIGNAL PROCESSING; VLSI CIRCUITS;

CLOCK AND DATA RECOVERY (CDR); INTER-SYMBOL INTERFERENCE (ISI); INTERNAL CLOCK SIGNALS; RECEIVER;

CMOS INTEGRATED CIRCUITS;

EID: 4544261378     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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