Low-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 8, 2009, Pages 2169-2180

  Arakali, Abhijith ^a   Gondi, Srikanth ^b   Hanumolu, Pavan Kumar ^a  

^a Oregon State University   (United States)

^b Kawasaki Microelectronics America Inc   (United States)

Author keywords

Phase locked loop; Ring oscillator; Split tunning; Supply noise sensitivity; Voltage regulator

Indexed keywords

DIGITAL CMOS; DOMINANT POLES; IN-PHASE; LOW FREQUENCY; LOW POWER; LOW-BANDWIDTH; NOISE REJECTION; NOISE SENSITIVITY; NOISE TRANSFER FUNCTION; OSCILLATOR PHASE NOISE; PHASE-LOCKED LOOP; POWER CONSUMPTION; POWER DISSIPATION; POWER SUPPLY; RING OSCILLATOR; SPLIT-TUNNING; SUPPLY-NOISE SENSITIVITY; WORST CASE;

ACOUSTIC NOISE; ARCHITECTURAL DESIGN; DELAY CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER TRANSMISSION NETWORKS; ELECTRIC POWER UTILIZATION; JITTER; OPTICAL DEVICES; OSCILLATORS (ELECTRONIC); PIEZOELECTRIC ACTUATORS; POLES; SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL; VOLTAGE STABILIZING CIRCUITS;

PHASE LOCKED LOOPS;

EID: 68549101796     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2022916     Document Type: Article

References (25)

1. T. H. Lee and A. Hajimiri, "Oscillator phase noise: A tutorial," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
2. A. Arakali, S. Gondi, and P. K. Hanumolu, "A 0.5-to-2.5 GHz supply-regulated PLL with noise sensitivity of - 28 dB," in Proc. IEEE Custom Integrated Circuits Conf., 2008, pp. 443-446.
3. V. von Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, "A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1715-1722, Nov. 1996.
4. K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, Y. Li, and S. Sidiropoulos, "A 0.44-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 747-754, May 2003.
5. S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers," in Symp. VLSI Circuits Dig., 2000, pp. 124-127.
6. E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, "Replica compensated linear regulators for supply-regulated phase-locked loops," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413-424, Feb. 2006.
7. P. K. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, "Analysis of charge-pump phase-locked loops," IEEE Trans. Circuits Syst. I, Reg. Papers, pp. 1665-1674, Sep. 2004.
8. J. Kim, D. Jones, and M. Horowitz, "Variable domain transformation for linear PAC analysis of mixed-signal systems," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 2007, pp. 887-894.
9. M. S. J. Steyaert and W. M. C. Sansen, "Power supply rejection ratio in operational transconductance amplifiers," IEEE Trans. Circuits Syst., pp. 1077-1084, Sep. 1990.
10. P. K. Hanumolu, G. Wei, and U. Moon, "A wide-tracking range clock and data recovery circuit," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 425-439, Feb. 2008.
11. S. Williams, H. Thompson, M. Hufford, and E. Naviasky, "An improved CMOS ring oscillator PLL with less than 4 ps rms accumulated jitter," in Proc. IEEE Custom Integrated Circuits Conf., 2004, pp. 151-154.
12. W. B. Wilson, U. Moon, K. R. Lakshmikumar, and L. Dai, "A CMOS self-calibrating frequency synthesizer," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1437-1444, Oct. 2000.
13. G. W. den Besten and B. Nauta, "Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 956-962, Jul. 1998.
14. E. Alon, "Measurement and regulation of on-chip power supply noise," Ph.D. dissertation, Stanford Univ., Stanford, CA, Dec. 2006.
15. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 10, pp. 1433-1439, Oct. 1989.
16. M. Mansuri, D. Liu, and C. K. K. Yang, "Fast frequency acquisition phase-frequency detectors for GSamples/s phase-locked loops," IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1331-1334, Oct. 2002.
17. P. Larsson, "A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1951-1960, Dec. 1999.
18. J. F. Parker, D. Weinlader, and J. L. Sonntag, "A 15 mW 3.125 GHz PLL for serial backplane transceivers in 0.13 μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2005, pp. 412-413.
19. M. Johnson and E. Hudson, "A variable delay line PLL for CPU-coprocessor synchronization," IEEE J. Solid-State Circuits, vol. 23, no. 10, pp. 1218-1223, Oct. 1988.
20. M. Mansuri and C. K. K. Yang, "A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804-1812, Nov. 2003.
21. J. M. Ingino, "A 4 GHz 40 dB PSRR PLL for an SOC application," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 392-393.
22. I. A. Young, J. K. Greason, and K. L. Wong, "A PLL clock generator 5-100 MHz lock range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, Nov. 1992.
23. J. G. Maneatis, "Low-jitter process independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
24. K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, T. Sato, K. Nakamura, and M. Yamashina, "A 0.1 μm CMOS, 1.2 V, 2 GHz phase-locked-loop with gain compensation VCO," in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 213-216.
25. H. T. Ahn and D. J. Allstot, "A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 450-454, Mar. 2000.