A 4GHz 40dB PSRR PLL for an SOC application

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 392-393+469

  Ingino, J M ^a  

^a SiByte Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; FLIP FLOP CIRCUITS; OPERATIONAL AMPLIFIERS; VARIABLE FREQUENCY OSCILLATORS; VOLTAGE REGULATORS;

POWER-SUPPLY-REJECTION RATIOS (PSRR); SYSTEM-ON-A-CHIP (SOC) APPLICATIONS;

PHASE LOCKED LOOPS;

EID: 0035054913     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A high-speed low-power clock generator for a microprocessor application
2. A 2-1600MHz 1.2-2.5V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction
3. A fast-settling CMOS op amp for SC circuits with 90-dB DC gain