A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 443-446

  Arakali, Abhijith ^a   Gondi, Srikanth ^b   Hanumolu, Pavan Kumar ^a  

^a Oregon State University   (United States)

^b Kawasaki Microelectronics America Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSES; NOISE REJECTIONS; NOISE SENSITIVITIES; POWER CONSUMPTIONS;

ACOUSTIC NOISE; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); PIEZOELECTRIC ACTUATORS;

PHASE LOCKED LOOPS;

EID: 57849167962     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672116     Document Type: Conference Paper

References (5)

1. V. von Kaenel et al., "A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation," IEEE J. Solid-State Circuits, vol. 31, pp. 1715-1722, Nov. 1996.
2. K. Chang et al., "A 0.44-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs," IEEE J. Solid-State Circuits,vol. 38, pp. 747-754, May 2003.
3. S. Sidiropouloset al., "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS Buffers," Symp. VLSI Circuits Dig., pp. 124-127, June 2000.
4. E. Alon et al., "Replica compensated linear regulators for supply-regulated phase-locked loops," IEEE J. Solid-State Circuits, vol. 41, pp. 413 - 424, Feb. 2006.
5. M. Johnson and E. Hudson, "A variable delay line PLL for CPU-coprocessor synchronization," IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, October 1988.