-
1
-
-
0037418895
-
Ultrahigh-density nanowire lattices and circuits
-
Apr
-
N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff, and J. R. Heath, "Ultrahigh-density nanowire lattices and circuits," Science, vol. 300, no. 5616, pp. 112-115, Apr. 2003.
-
(2003)
Science
, vol.300
, Issue.5616
, pp. 112-115
-
-
Melosh, N.A.1
Boukai, A.2
Diana, F.3
Gerardot, B.4
Badolato, A.5
Petroff, P.M.6
Heath, J.R.7
-
2
-
-
0035902938
-
Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species
-
Aug
-
Y. Cui, Q. Wei, H. Park, and C. M. Lieber, "Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species," Science, vol. 293, no. 5533, pp. 1289-1292, Aug. 2001.
-
(2001)
Science
, vol.293
, Issue.5533
, pp. 1289-1292
-
-
Cui, Y.1
Wei, Q.2
Park, H.3
Lieber, C.M.4
-
3
-
-
38049148246
-
Silicon nanowires as efficient thermoelectric materials
-
Jan
-
A. I. Boukai, Y. Bunimovich, J. Tahir-Kheli, J.-K. Yu, W. A. Goddard, III, and J. R. Heath, "Silicon nanowires as efficient thermoelectric materials," Nature, vol. 451, no. 7175, pp. 168-171, Jan. 2008.
-
(2008)
Nature
, vol.451
, Issue.7175
, pp. 168-171
-
-
Boukai, A.I.1
Bunimovich, Y.2
Tahir-Kheli, J.3
Yu, J.-K.4
Goddard III, W.A.5
Heath, J.R.6
-
4
-
-
0035793378
-
Functional nanoscale electronic devices assembled using silicon nanowire building blocks
-
Feb
-
Y. Cui and C. M. Lieber, "Functional nanoscale electronic devices assembled using silicon nanowire building blocks," Science, vol. 291, no. 5505, pp. 851-853, Feb. 2001.
-
(2001)
Science
, vol.291
, Issue.5505
, pp. 851-853
-
-
Cui, Y.1
Lieber, C.M.2
-
5
-
-
56549083690
-
Scaling of nanowire transistors
-
Nov
-
B. Yu, L. Wang, Y. Yuan, P. M. Asbeck, and Y. Thur, "Scaling of nanowire transistors," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2846-2858, Nov. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.11
, pp. 2846-2858
-
-
Yu, B.1
Wang, L.2
Yuan, Y.3
Asbeck, P.M.4
Thur, Y.5
-
6
-
-
85008006353
-
Vertically stacked SiGe nanowire array channel CMOS transistors
-
Mar
-
W. W. Fang, N. Singh, L. K. Bera, H. S. Nguyen, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "Vertically stacked SiGe nanowire array channel CMOS transistors," IEEE Electron Device Lett., vol. 28, no. 3, pp. 211-213, Mar. 2007.
-
(2007)
IEEE Electron Device Lett
, vol.28
, Issue.3
, pp. 211-213
-
-
Fang, W.W.1
Singh, N.2
Bera, L.K.3
Nguyen, H.S.4
Rustagi, S.C.5
Lo, G.Q.6
Balasubramanian, N.7
Kwong, D.-L.8
-
7
-
-
33646271349
-
High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices
-
May
-
N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-385, May 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.5
, pp. 383-385
-
-
Singh, N.1
Agarwal, A.2
Bera, L.K.3
Liow, T.Y.4
Yang, R.5
Rustagi, S.C.6
Tung, C.H.7
Kumar, R.8
Lo, G.Q.9
Balasubramanian, N.10
Kwong, D.-L.11
-
8
-
-
56649122022
-
Si, SiGe nanowire devices by top-down technology and their applications
-
Nov
-
N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "Si, SiGe nanowire devices by top-down technology and their applications," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3107-3118, Nov. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.11
, pp. 3107-3118
-
-
Singh, N.1
Buddharaju, K.D.2
Manhas, S.K.3
Agarwal, A.4
Rustagi, S.C.5
Lo, G.Q.6
Balasubramanian, N.7
Kwong, D.-L.8
-
9
-
-
0027567658
-
Mechanical stability and adhesion of microstructures under capillary forces - Part I : Basic theory
-
Mar
-
C. H. Mastrangelo and C. H. Hsu, "Mechanical stability and adhesion of microstructures under capillary forces - Part I : Basic theory," J. Microelectromech. Syst., vol. 2, no. 1, pp. 33-43, Mar. 1993.
-
(1993)
J. Microelectromech. Syst
, vol.2
, Issue.1
, pp. 33-43
-
-
Mastrangelo, C.H.1
Hsu, C.H.2
-
11
-
-
33847734326
-
High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability
-
S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D.-S. Shin, K.-H. Lee, H. S. Park, J. N. Han, C. J. Park, J.-B. Park, D.-W. Kim, D. Park, and B.-I. Ryu, "High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability," in IEDM Tech. Dig., 2005, pp. 717-720.
-
(2005)
IEDM Tech. Dig
, pp. 717-720
-
-
Suk, S.D.1
Lee, S.-Y.2
Kim, S.-M.3
Yoon, E.-J.4
Kim, M.-S.5
Li, M.6
Oh, C.W.7
Yeo, K.H.8
Kim, S.H.9
Shin, D.-S.10
Lee, K.-H.11
Park, H.S.12
Han, J.N.13
Park, C.J.14
Park, J.-B.15
Kim, D.-W.16
Park, D.17
Ryu, B.-I.18
-
12
-
-
51949099572
-
TSNWFET for SRAM cell application: Performance variation and process dependency
-
S. D. Suk, Y. Y. Yeoh, M. Li, K. H. Yeo, S.-H. Kim, D.-W. Kim, D. Park, and W.-S. Lee, "TSNWFET for SRAM cell application: Performance variation and process dependency," in VLSI Symp. Tech. Dig., 2008, pp. 38-39.
-
(2008)
VLSI Symp. Tech. Dig
, pp. 38-39
-
-
Suk, S.D.1
Yeoh, Y.Y.2
Li, M.3
Yeo, K.H.4
Kim, S.-H.5
Kim, D.-W.6
Park, D.7
Lee, W.-S.8
-
13
-
-
50249165347
-
Examination of additive mobility enhancements for uniaxial stress combined with biaxially strained Si, biaxially strained SiGe and Ge channel MOSFETs
-
O. Weber, T. Irisawa, T. Numata, M. Harada, N. Taoka, Y. Yamashita, T. Yamamoto, N. Sugiyama, M. Takenaka, and S. Takagi, "Examination of additive mobility enhancements for uniaxial stress combined with biaxially strained Si, biaxially strained SiGe and Ge channel MOSFETs," in IEDM Tech. Dig., 2007, pp. 719-722.
-
(2007)
IEDM Tech. Dig
, pp. 719-722
-
-
Weber, O.1
Irisawa, T.2
Numata, T.3
Harada, M.4
Taoka, N.5
Yamashita, Y.6
Yamamoto, T.7
Sugiyama, N.8
Takenaka, M.9
Takagi, S.10
-
14
-
-
34247866290
-
Quasi-3-D velocity saturation model for multiple-gate MOSFETs
-
May
-
J.-W. Han, C.-H. Lee, D. Park, and Y-K. Choi, "Quasi-3-D velocity saturation model for multiple-gate MOSFETs," IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1165-1170, May 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.5
, pp. 1165-1170
-
-
Han, J.-W.1
Lee, C.-H.2
Park, D.3
Choi, Y.-K.4
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