Improvement of memory state misidentification caused by trap-assisted GIDL current in a SONOS-TFT memory device

IEEE Electron Device Letters

Volumn 30, Issue 8, 2009, Pages 834-836

  Chen, Te Chih ^a   Chang, Ting Chang ^a,b   Jian, Fu Yen ^a   Chen, Shih Ching ^a   Lin, Chia Sheng ^a   Lee, Ming Hsien ^c   Chen, Jim Shone ^c   Shih, Ching Chieh ^c  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^c AU OPTRONICS CORPORATION   (Taiwan)

Author keywords

Memories; Thin film transistors

Indexed keywords

BAND-TO-BAND HOT HOLE; DRAIN OVERLAP; FOWLER-NORDHEIM; GATE-INDUCED DRAIN LEAKAGE; HOT HOLES; MEMORIES; MEMORY DEVICE; MEMORY STATE; NITRIDE LAYERS; NON-VOLATILE MEMORIES; POLYCRYSTALLINE; PROGRAM OPERATION; SILICON-OXIDE-NITRIDE-OXIDE-SILICON STRUCTURES;

LEAKAGE CURRENTS; NITRIDES; SILICON OXIDES; THIN FILM TRANSISTORS; THIN FILMS;

DRAIN CURRENT;

EID: 68249143291     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2023827     Document Type: Article

References (14)

1. T. Aoyama, K. Ogawa, Y. Mochizuki, and N. Konishi, "Inverse staggered poly-Si and amorphous Si double structure TFTs for LCD panels with peripheral driver circuits integration," IEEE Trans. Electron Devices, vol. 43, no. 5, pp. 701-705, May 1996.
2. A. J. Walker, S. Nallamothu, E.-H. Chen, M. Mahajani, S. B. Herner, M. Clark, J. M. Cleeves, S. V. Dunton, V. L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, "3D TFT-SONOS memory cell for ultra-high density file storage applications," in VLSI Symp. Tech. Dig., Jun. 2003, pp. 29-30.
3. K. Yoneda, R. Yokoyama, and T. Yamada, "Development trends of LTPS TFT LCDs for mobile applications," in Proc. Symp. VLSI Circuits, 2001, pp. 85-90.
4. H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, H. Murai, and H. Nagata, "Low power consumption TFT-LCD with dynamic memory embedded in pixels," in Proc. SID, 2001, pp. 280-283.
5. P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells - An overview," Proc. IEEE, vol. 85, no. 8, pp. 1248-1271, Aug. 1997.
6. J. W. Han, S. W. Ryu, S. J. Choi, and Y. K. Choi, "Gate-induced drain-leakage (GIDL) programming method for soft-programming-free operation in Unified RAM (URAM)," IEEE Electron Device Lett., vol. 30, no. 2, pp. 189-191, Feb. 2009.
7. E. Yoshida and T. Tanaka, "A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high embedded memory," IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006.
8. C. Chen and T. P. Ma, "A new source-side erase algorithm to reduce wordline disturb problem in flash EPROM," in VLSI Symp. Tech. Dig. 1995, pp. 321-325.
9. S. R. Kim, K. J. Han, J. Lee, T. Zhou, K. S. Lee, P. Liu, P. Y. Lee, and H. C. Tseng, "Investigation of GIDL current injection disturb mechanism in two-transistor-eNVM memory devices," in Proc. Integr. Rel. Workshop Final Rep., 2008, pp. 40-43.
10. C. C. Yeh, T. Wang, W. J. Tsai, T. C. Lu, Y. Y. Liao, and H. Y. Chen, "A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell," IEEE Electron Device Lett., vol. 25, no. 9, pp. 643-645, Sep. 2004.
11. J. A. Butts and G. Sohi, "A static power model for architects," in Proc. 33rd ACM/IEEE Int. Symp. Microarchitecture, 2000, pp. 191-201.
12. J. H. Chen, S.-C. Wong, and Y.-H. Wang, "An analytical three-terminal band-to-band tunneling model on GIDL in MOSFET," IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1400-1405, Jul. 2001.
13. I. Bloom, P. Pavan, and B. Eitan, "NROMTM - A new technology for non-volatile memory products," Solid State Electron., vol. 46, no. 11, pp. 1757-1763, Nov. 2002.
14. H. T. Lue, Y. T. Hsiao, Y. H. Shih, E. K. Lai, K. Y. Hsieh, R. Liu, and C. Y. Lu, "Study of charge loss mechanism of SONOS-type devices using hothole erase and methods to improve the charge retention," in Proc. 44th IEEE Annu. Int. Rel. Phys. Symp., San Jose, CA, 2006, pp. 523-529.