A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

IEEE Electron Device Letters

Volumn 25, Issue 9, 2004, Pages 643-645

  Yeh, Chih Chieh ^a,b   Wang, Tahui ^a,b   Tsai, Wen Jer ^a,b   Lu, Tao Cheng ^a   Liao, Yi Ying ^a   Chen, Hung Yueh ^a   Zous, Nian Kai ^a   Ting, Wenchi ^a   Ku, Joseph ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; DIELECTRIC MATERIALS; ELECTRIC CHARGE; FLASH MEMORY; GATES (TRANSISTOR); HOLE TRAPS; LEAKAGE CURRENTS; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE;

BAND-TO-BAND HOT HOLE; FLASH MEMORY CELL; NITRIDE TRAPPING STORAGE; OVERERASURE;

MOSFET DEVICES;

EID: 4444348629     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.833596     Document Type: Article

References (13)

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