-
1
-
-
84966670525
-
Architecture design of reconfigurable pipelined datapaths
-
Atlanta
-
D. Cronquist, C. Fisher, M. Figueroa, P. Franklin, and C. Ebeling, "Architecture design of reconfigurable pipelined datapaths," The Conference on Advanced Research in VLSI, Atlanta, 1999.
-
(1999)
The Conference on Advanced Research in VLSI
-
-
Cronquist, D.1
Fisher, C.2
Figueroa, M.3
Franklin, P.4
Ebeling, C.5
-
3
-
-
0032655186
-
HSRA: High-speed, hierarchical synchronous reconfigurable array
-
W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon, "HSRA: high-speed, hierarchical synchronous reconfigurable array," Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, 1999.
-
(1999)
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays
-
-
Tsu, W.1
Macy, K.2
Joshi, A.3
Huang, R.4
Walker, N.5
Tung, T.6
Rowhani, O.7
George, V.8
Wawrzynek, J.9
Dehon, A.10
-
4
-
-
0032674517
-
PipeRench: A coprocessor for streaming multimedia acceleration
-
S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer, "PipeRench: a Coprocessor for Streaming Multimedia Acceleration," 26th International Symposium on Computer Architecture (ISCA99), 1999.
-
(1999)
26th International Symposium on Computer Architecture (ISCA99)
-
-
Goldstein, S.C.1
Schmit, H.2
Moe, M.3
Budiu, M.4
Cadambi, S.5
Taylor, R.R.6
Laufer, R.7
-
5
-
-
0038256684
-
PipeRoute: A pipeliningaware router for FPGAs
-
A. Sharma, C. Ebeling, and S. Hauck, "PipeRoute: A PipeliningAware Router for FPGAs," University of Washington, EE Department Technical Report UWEETR-0018, 2002.
-
(2002)
University of Washington, EE Department Technical Report
, vol.UWEETR-0018
-
-
Sharma, A.1
Ebeling, C.2
Hauck, S.3
-
6
-
-
0006065427
-
Improved approximation guarantees for minimum-weight k-trees and prize-collecting salesmen
-
Las Vegas, Nevada, United States
-
B. Awerbuch, Y. Azar, A. Blum, and S. Vempala, "Improved approximation guarantees for minimum-weight k-trees and prize-collecting salesmen," Proceedings of the twenty-seventh annual ACM symposium on Theory of computing, Las Vegas, Nevada, United States, 1995.
-
(1995)
Proceedings of the Twenty-seventh Annual ACM Symposium on Theory of Computing
-
-
Awerbuch, B.1
Azar, Y.2
Blum, A.3
Vempala, S.4
-
7
-
-
0034174187
-
PipeRench: A reconfigurable architecture and compiler
-
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. Taylor, "PipeRench: A Reconfigurable Architecture and Compiler," IEEE Computer, vol. 33, 2000.
-
(2000)
IEEE Computer
, vol.33
-
-
Goldstein, S.C.1
Schmit, H.2
Budiu, M.3
Cadambi, S.4
Moe, M.5
Taylor, R.6
-
8
-
-
0034187952
-
MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications
-
H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. Chaves Filho, "MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications," Computers, IEEE Transactions on, vol. 49, pp. 465-481, 2000.
-
(2000)
Computers, IEEE Transactions on
, vol.49
, pp. 465-481
-
-
Singh, H.1
Lee, M.-H.2
Lu, G.3
Kurdahi, F.J.4
Bagherzadeh, N.5
Chaves Filho, E.M.6
-
10
-
-
0009755242
-
Iterative Modulo Scheduling
-
B. Rau, "Iterative Modulo Scheduling," HP Labs Technical Report HPL-94-115, 1994.
-
(1994)
HP Labs Technical Report
, vol.HPL-94-115
-
-
Rau, B.1
-
12
-
-
0029534183
-
Placement and routing tools for the Triptych FPGA
-
C. Ebeling, L. McMurchie, S. A. Hauck, and S. Burns, "Placement and routing tools for the Triptych FPGA," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, pp. 473-482, 1995.
-
(1995)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.3
, pp. 473-482
-
-
Ebeling, C.1
McMurchie, L.2
Hauck, S.A.3
Burns, S.4
-
15
-
-
0022094206
-
Generalized best-first search strategies and the optimality af A*
-
R. Dechter and J. Pearl, "Generalized best-first search strategies and the optimality af A*," J. ACM, vol. 32, pp. 505-536, 1985.
-
(1985)
J. ACM
, vol.32
, pp. 505-536
-
-
Dechter, R.1
Pearl, J.2
-
16
-
-
0031638178
-
A fast routability-driven router for FPGAs
-
Monterey, California, United States
-
J. S. Swartz, V. Betz, and J. Rose, "A fast routability-driven router for FPGAs," 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, Monterey, California, United States, 1998.
-
(1998)
1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays
-
-
Swartz, J.S.1
Betz, V.2
Rose, J.3
-
18
-
-
2442628327
-
Exploration of pipelined FPGA interconnect structures
-
Monterey, CA
-
A. Sharma, K. Compton, C. Ebeling, and S. Hauck, "Exploration of Pipelined FPGA Interconnect Structures," Twefth International Symposium on Field-Programmable Gate Arrays, Monterey, CA, 2004.
-
(2004)
Twefth International Symposium on Field-programmable Gate Arrays
-
-
Sharma, A.1
Compton, K.2
Ebeling, C.3
Hauck, S.4
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