메뉴 건너뛰기




Volumn , Issue , 2007, Pages 323-330

Virtualization on the Tartan reconfigurable architecture

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); ENERGY EFFICIENCY; FABRICS;

EID: 48149099251     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380667     Document Type: Conference Paper
Times cited : (13)

References (16)
  • 4
    • 0028768023 scopus 로고
    • A High-Performance Microarchitecture with Hardware-Programmable Functional Units
    • IEEE/ACM, Nov
    • R. Razdan and M. D. Smith, "A High-Performance Microarchitecture with Hardware-Programmable Functional Units," in IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE/ACM, Nov. 1994, pp. 172-80.
    • (1994) IEEE/ACM International Symposium on Microarchitecture (MICRO) , pp. 172-180
    • Razdan, R.1    Smith, M.D.2
  • 5
    • 0033884609 scopus 로고    scopus 로고
    • Co-synthesis to a hybrid RISC/FPGA architecture
    • M. B. Gokhale, J. M. Stone, and E. Gomersall, "Co-synthesis to a hybrid RISC/FPGA architecture," J. VLSI Signal Process. Syst., vol. 24, no. 2-3, pp. 165-180, 2000.
    • (2000) J. VLSI Signal Process. Syst , vol.24 , Issue.2-3 , pp. 165-180
    • Gokhale, M.B.1    Stone, J.M.2    Gomersall, E.3
  • 6
    • 0033703884 scopus 로고    scopus 로고
    • CHI-MAERA: A high-performance architecture with a tightlycoupled reconfigurable unit
    • International Symposium on Computer Architecture ISCA, ACM Press
    • A. Z. Ye, A. Moshovos, S. Hauck, and P. Banerjee, "CHI-MAERA: A high-performance architecture with a tightlycoupled reconfigurable unit," in International Symposium on Computer Architecture (ISCA), ser. ACM Computer Architecture News. ACM Press, 2000.
    • (2000) ser. ACM Computer Architecture News
    • Ye, A.Z.1    Moshovos, A.2    Hauck, S.3    Banerjee, P.4
  • 11
    • 33846513045 scopus 로고
    • Standard Performance Evaluation Corp
    • SPEC INT 95 Benchmark Suite, Standard Performance Evaluation Corp., 1995.
    • (1995) SPEC INT 95 Benchmark Suite
  • 16
    • 0036382691 scopus 로고    scopus 로고
    • Config. prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation
    • Z. Li and S. Hauck, "Config. prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation," in Proceedings of the Int'l Symposium on Field-Programmable Gate Arrays (FPGA), 2002, pp. 187-195.
    • (2002) Proceedings of the Int'l Symposium on Field-Programmable Gate Arrays (FPGA) , pp. 187-195
    • Li, Z.1    Hauck, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.