Co-integration of 2 mV/dec subthreshold slope impact ionization MOS (I-MOS) with CMOS

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn 2006-January, Issue , 2006, Pages 303-306

  Mayer, F ^a   Le Royer, C ^a   Le Carval, G ^a   Tabone, C ^a   Clavelier, L ^a   Deleonibus, S ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

COINTEGRATION; CONVENTIONAL MOSFETS; DIFFUSION PHENOMENA; IMPACT IONIZATION MOS; P-MOSFETS; SILICON ON INSULATOR WAFERS; STANDARD CMOS PROCESS; SUBTHRESHOLD SLOPE;

IMPACT IONIZATION;

EID: 84957890418     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/essder.2006.307698     Document Type: Conference Paper

References (12)

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