A 20-Gb/s full-rate 27-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 221-224

  Kim, Jeong Kyoum ^a   Kim, Jaeha ^b   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

^b RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK BUFFER; CLOCK DISTRIBUTION; CLOCK-JITTER; CMOS PROCESS; INDUCTIVE PEAKING; MEASURED DATA; NEGATIVE FEEDBACK; PRBS GENERATOR; XOR GATES;

CLOCKS; FEEDBACK; PHASE LOCKED LOOPS;

JITTER;

EID: 67649961679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708768     Document Type: Conference Paper

References (10)

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