A 26.5-37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 148-151

  Kim, Jeong Kyoum ^a   Kim, Jaeha ^a   Lee, Sang Yoon ^a   Kim, Suhwan ^a   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS;

INDUCTIVE PEAKING; OPERATING FREQUENCIES; SERIAL LINK; SOLID-STATE CIRCUITS CONFERENCE;

FREQUENCY DIVIDING CIRCUITS;

EID: 51349142773     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425752     Document Type: Conference Paper

References (6)

1. J. Kim, et al., "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13 ?m CMOS," IEEE J. Solid State Circuits, pp.899-908, Apr. 2006.
2. J. Kim, et al., "Circuit techniques for a 40-Gb/s transmitter in 0.13 ?μm CMOS," IEEE ISSCC Dig. of Tech. Papers, pp. 150-151, Feb. 2005.
3. S.Galal, B.Razavi, "10Gb/s limiting amplifier and laser/Modulator driver in 0.18?m CMOS technology," IEEE ISSCC Dig. of Tech. Papers, pp. 188 - 189, Feb. 2003.
4. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. New York: Cambridge Univ. Press, 1998.
5. U. Singh, and M. M. Green, "High-Frequency CML Clock Divider in 0.13 μ m CMOS Operating Up to 38GHz," IEEE J. Solid State Circuits, Vol. 40, No. 8, pp. 1658-1661, Aug. 2005.
6. M. Tiebout, "A CMOS Direct Injection-Locked Oscillator Topology as High-Frequency Low-Power Frequency Divider," IEEE J. Solid-State Circuits, vol. 39, No. 7 pp. 1170-1174, JUL. 2004.