20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 189-192

  Singh, Pratap Narayan ^a   Kumar, Ashish ^a   Debnath, Chandrajit ^a   Malik, Rakesh ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

ADAPTIVE BIASING; CROSS-COUPLED; DIGITAL CMOS; LOW POWER; NOVEL TECHNIQUES; PIPELINED ADCS; POWER EFFICIENCY; SETTLING BEHAVIOR;

CMOS INTEGRATED CIRCUITS;

EID: 67649956070     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405710     Document Type: Conference Paper

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