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Volumn 41, Issue 7, 2006, Pages 1589-1594

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

Author keywords

Amplifier sharing; Analog to digital conversion; Analog to digital converter (ADC); Wireless receiver

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; INTEGRAL EQUATIONS; SIGNAL TO NOISE RATIO;

EID: 33746349851     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.873888     Document Type: Conference Paper
Times cited : (62)

References (14)
  • 1
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    • Jul.
    • L. Sumanen, M. Waltari, and K. A. I. Halonen, "A 10-bit 200-MS/s CMOS parallel pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1048-1055, Jul. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.36 , Issue.7 , pp. 1048-1055
    • Sumanen, L.1    Waltari, M.2    Halonen, K.A.I.3
  • 5
    • 0025562755 scopus 로고
    • A 10-b 15-MHz CMOS recycling two-itep A/D converter
    • Dec.
    • B.-S. Song, S.-H. Lee, and M. F. Tompsett, "A 10-b 15-MHz CMOS recycling two-itep A/D converter," IEEE J. Solid-State Circuits, vol. 25, no, 12, pp. 1328-1338, Dec. 1990.
    • (1990) IEEE J. Solid-state Circuits , vol.25 , Issue.12 , pp. 1328-1338
    • Song, B.-S.1    Lee, S.-H.2    Tompsett, M.F.3
  • 6
    • 0037319649 scopus 로고    scopus 로고
    • 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture
    • Feb.
    • D. Miyazaki, S. Kawahito, and M. Furuta, "10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture," IEEE J. Solid-State Circuits, vol 38, no. 2, pp. 369-373, Feb. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , Issue.2 , pp. 369-373
    • Miyazaki, D.1    Kawahito, S.2    Furuta, M.3
  • 9
    • 0030106088 scopus 로고    scopus 로고
    • A power optimized 13-b 5-Miamples/s pipelined analog-digital converter in 1.2 μ CMOS
    • Mar.
    • D. Cline and P. Gray, "A power optimized 13-b 5-Miamples/s pipelined analog-digital converter in 1.2 μ CMOS "IEEE J. Solid-State Circuits, vol. 31, pp. 294-303, Mar. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , pp. 294-303
    • Cline, D.1    Gray, P.2
  • 10
    • 0032597761 scopus 로고    scopus 로고
    • A 2 Vpp linear inputrange fully balanced CMOS transconductor and its application to a 2.5 v 2.5 MHz Gm-C LPF
    • May
    • T. Itakura, T. Ueno, H. Tanimoto, and T. Arai, "A 2 Vpp linear inputrange fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF," in Proc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 509-512.
    • (1999) Proc. IEEE Custom Integrated Circuits Conf. , pp. 509-512
    • Itakura, T.1    Ueno, T.2    Tanimoto, H.3    Arai, T.4
  • 12
    • 0036912842 scopus 로고    scopus 로고
    • A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
    • Dec.
    • S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst, and S. H. Lewis, "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1618-1627, Dec. 2002.
    • (2002) IEEE J. Solid-state Circuits , vol.37 , Issue.12 , pp. 1618-1627
    • Jamal, S.M.1    Fu, D.2    Chang, N.C.-J.3    Hurst, P.J.4    Lewis, S.H.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.