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A 10 b 125 MS/s 40 mW pipelined ADC in 0.18 μma CMOS
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A 1.2 v 220 MS/s 10 b pipeline ADC implemented in 0.13 μm digital CMOS
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A 10-b 15-MHz CMOS recycling two-itep A/D converter
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Oct.
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Dec.
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Mar.
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A 2 Vpp linear inputrange fully balanced CMOS transconductor and its application to a 2.5 v 2.5 MHz Gm-C LPF
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A family of differential nMOS analog circuits for a PCM codec filter chip
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Dec.
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A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
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Dec.
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Splitting the unit delay
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Jan.
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T. I. Laakso, V. Valimaki, M. Karjalainen, and U. K. Laine, "Splitting the unit delay," IEEE Signal Processing Mag., vol 13, no. 1, pp. 30-60, Jan. 1996.
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Laakso, T.I.1
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