-
1
-
-
0036868980
-
Low-temperature polycrystalline silicon thin-film transistor technologies for system-on-glass displays
-
Nov
-
S. Uchikoga, "Low-temperature polycrystalline silicon thin-film transistor technologies for system-on-glass displays," MRS Bull., vol. 27, no. 11, pp. 881-886, Nov. 2002.
-
(2002)
MRS Bull
, vol.27
, Issue.11
, pp. 881-886
-
-
Uchikoga, S.1
-
2
-
-
0141426842
-
3D TFT-SONOS memory cell for ultra-high density file storage applications
-
A. J. Walker, S. Nallamothu, E.-H. Chen, M. Mahajani, S. B. Herner, M. Clark, J. M. Cleeves, S. V. Dunton, V. L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, "3D TFT-SONOS memory cell for ultra-high density file storage applications," in VLSI Symp. Tech. Dig., 2003, pp. 29-30.
-
(2003)
VLSI Symp. Tech. Dig
, pp. 29-30
-
-
Walker, A.J.1
Nallamothu, S.2
Chen, E.-H.3
Mahajani, M.4
Herner, S.B.5
Clark, M.6
Cleeves, J.M.7
Dunton, S.V.8
Eckert, V.L.9
Gu, J.10
Hu, S.11
Knall, J.12
Konevecki, M.13
Petti, C.14
Radigan, S.15
Raghuram, U.16
Vienna, J.17
Vyvoda, M.A.18
-
3
-
-
37549041289
-
Multiple-gate CMOS thin-film transistor with polysilicon nanowire
-
Jan
-
M. Im, J.-W. Han, H. Lee, L.-E. Yu, S. Kim, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y.-K. Choi, "Multiple-gate CMOS thin-film transistor with polysilicon nanowire," IEEE Electron Device Lett., vol. 29, no. 1, pp. 102-105, Jan. 2008.
-
(2008)
IEEE Electron Device Lett
, vol.29
, Issue.1
, pp. 102-105
-
-
Im, M.1
Han, J.-W.2
Lee, H.3
Yu, L.-E.4
Kim, S.5
Jeon, S.C.6
Kim, K.H.7
Lee, G.S.8
Oh, J.S.9
Park, Y.C.10
Lee, H.M.11
Choi, Y.-K.12
-
4
-
-
26444483307
-
A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel
-
Sep
-
H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang, "A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel," IEEE Electron Device Lett., vol. 26, no. 9, pp. 643-645, Sep. 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.9
, pp. 643-645
-
-
Lin, H.C.1
Lee, M.H.2
Su, C.J.3
Huang, T.Y.4
Lee, C.C.5
Yang, Y.S.6
-
5
-
-
33947244195
-
Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels
-
Oct
-
H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, "Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2471-2477, Oct. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.10
, pp. 2471-2477
-
-
Lin, H.C.1
Lee, M.H.2
Su, C.J.3
Shen, S.W.4
-
6
-
-
47249092862
-
A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate
-
Jul
-
H. C. Lin, H. H. Hsu, C. J. Su, and T. Y. Huang, "A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate," IEEE Electron Device Lett., vol. 29, no. 7, pp. 718-720, Jul. 2008.
-
(2008)
IEEE Electron Device Lett
, vol.29
, Issue.7
, pp. 718-720
-
-
Lin, H.C.1
Hsu, H.H.2
Su, C.J.3
Huang, T.Y.4
-
7
-
-
0020796133
-
Effects of grain boundaries on the channel conductance of SOI MOSFETs
-
Aug
-
J. G. Fossum and A. Ortiz-Conde, "Effects of grain boundaries on the channel conductance of SOI MOSFETs," IEEE Trans. Electron Devices vol. ED-30, no. 8, pp. 933-940, Aug. 1983.
-
(1983)
IEEE Trans. Electron Devices
, vol.ED-30
, Issue.8
, pp. 933-940
-
-
Fossum, J.G.1
Ortiz-Conde, A.2
-
8
-
-
0029409727
-
3 plasma passivation on polysilicon thin-film transistors
-
Nov
-
3 plasma passivation on polysilicon thin-film transistors," IEEE Electron Device Lett., vol. 16, no. 11, pp. 503-505, Nov. 1995.
-
(1995)
IEEE Electron Device Lett
, vol.16
, Issue.11
, pp. 503-505
-
-
Wang, F.S.1
Tsai, M.J.2
Cheng, H.C.3
-
9
-
-
0032320827
-
Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D atomistic simulation study
-
Dec
-
A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D atomistic simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, Issue.12
, pp. 2505-2513
-
-
Asenov, A.1
-
10
-
-
77952646477
-
Ambipolar Schottky barrier poly-Si thin-film transistors with narrow channel width for improved performance
-
Jul
-
H. C. Lin, K. L. Yeh, M. H. Lee, W. Lee, W. J. Lin, and T. Y. Huang, "Ambipolar Schottky barrier poly-Si thin-film transistors with narrow channel width for improved performance," in Proc. AMLCD, Jul. 2003, p. 247.
-
(2003)
Proc. AMLCD
, pp. 247
-
-
Lin, H.C.1
Yeh, K.L.2
Lee, M.H.3
Lee, W.4
Lin, W.J.5
Huang, T.Y.6
-
11
-
-
49049088107
-
Characteristics of poly-Si nanowire transistors with multiple-gate configurations
-
H. H. Hsu, H. C. Lin, K. H. Lee, J. F. Huang, and T. Y. Huang, "Characteristics of poly-Si nanowire transistors with multiple-gate configurations," in Proc. Tech. Dig. VLSI Technol. Syst., Appl., 2008, pp. 101-102.
-
(2008)
Proc. Tech. Dig. VLSI Technol. Syst., Appl
, pp. 101-102
-
-
Hsu, H.H.1
Lin, H.C.2
Lee, K.H.3
Huang, J.F.4
Huang, T.Y.5
-
12
-
-
0035445204
-
A study of the threshold voltage variation for ultra-small bulk and SOI CMOS
-
Sep
-
K. Takeuchi, R. Koh, and T. Mogami, "A study of the threshold voltage variation for ultra-small bulk and SOI CMOS," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 1995-2001, Sep. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.9
, pp. 1995-2001
-
-
Takeuchi, K.1
Koh, R.2
Mogami, T.3
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