A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology

Nanotechnology

Volumn 20, Issue 24, 2009, Pages

  Zhao, Hong Quan ^a   Kasai, Seiya ^a,b   Shiratori, Yuta ^a   Hashizume, Tamotsu ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC LOGIC UNIT; CENTRAL PROCESSING UNITS; FUNDAMENTAL BUILDING BLOCKS; GAAS; GRAPH STRUCTURES; GRAPHICAL REPRESENTATIONS; NANOWIRE NETWORKS; OUTPUT WAVEFORM; ROOM TEMPERATURE; SCHOTTKY WRAP GATES; SIMPLE CIRCUITS; SUBGRAPHS; THRESHOLD VOLTAGE VARIATION; TOPOLOGY CONTROL; WET-CHEMICAL ETCHING;

BINARY DECISION DIAGRAMS; ELECTRIC WIRE; ELECTRON BEAMS; GALLIUM ALLOYS; GRAPHIC METHODS; NANOWIRES; SEMICONDUCTING GALLIUM; SWITCHING FUNCTIONS; TOPOLOGY;

LOGIC CIRCUITS;

NANOWIRE; GALLIUM; GALLIUM ARSENIDE; NANOMATERIAL; ORGANOARSENIC DERIVATIVE;

ARITHMETIC; ARTICLE; CHEMICAL ANALYSIS; CHEMICAL MODIFICATION; CHEMICAL STRUCTURE; CONTROLLED STUDY; DECISION MAKING; ELECTRIC POTENTIAL; ELECTRON BEAM; INTEGRATED CIRCUIT; NANODEVICE; NANOFABRICATION; NETWORK LEARNING; PRIORITY JOURNAL; ROOM TEMPERATURE; WAVEFORM; CHEMISTRY; CONFORMATION; CRYSTALLIZATION; ELECTRONICS; EQUIPMENT; EQUIPMENT DESIGN; INSTRUMENTATION; MACROMOLECULE; MATERIALS TESTING; MATHEMATICS; METHODOLOGY; NANOTECHNOLOGY; PARTICLE SIZE; SIGNAL PROCESSING; SURFACE PROPERTY; ULTRASTRUCTURE;

ARSENICALS; CRYSTALLIZATION; ELECTRONICS; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; GALLIUM; MACROMOLECULAR SUBSTANCES; MATERIALS TESTING; MATHEMATICS; MOLECULAR CONFORMATION; NANOSTRUCTURES; NANOTECHNOLOGY; PARTICLE SIZE; SIGNAL PROCESSING, COMPUTER-ASSISTED; SURFACE PROPERTIES;

EID: 67649312353     PISSN: 09574484     EISSN: 13616528     Source Type: Journal    
DOI: 10.1088/0957-4484/20/24/245203     Document Type: Article

References (35)

1. Yanushkevich S N, Miller D M, Shmerko V P and Stankovic R S 2006 Decision Diagram Techniques for Micro-and Nanoelectronic Design Handbook (Boca Raton, FL: CRC Press) and references there in
2. Hasegawa H and Kasai S 2001 Physica E 11 149
3. Kasai S and Hasegawa H 2002 IEEE Electron Device Lett. 23 446
4. Akers S B 1978 IEEE Trans. Comput. C-27 509
5. Asahi N, Akazawa M and Amemiya Y 1995 IEEE Trans. Electron Devices 42 1999
6. Kasai S, Yumoto M and Hasegawa H 2003 Solid State Electron. 47 199
7. Kasai S, Yumoto M, Sato T and Hasegawa H 2004 ECS Proc. 2004-13 125
8. Kasai S, Nakamura T, Shiratori Y and Tamura T 2007 J. Comput. Theor. Nanosci. 4 1120
9. Yoshikawa N, Tago H and Yoneyama K 1999 IEEE Trans. Appl. Supercond. 9 3161
10. Yoshikawa N, Matsuzaki F, Nakajima N, Fujiwara K, Yoda K and Kawasaki K 2003 IEEE Trans. Appl. Supercond. 13 441
11. Yumoto M, Kasai S and Hasegawa H 2002 Microelectron. Eng. 63 287
12. Kasai S and Hasegawa H 2002 Physica E 13 925
13. Eachempati S, Saripalli V, Vijaykrishnan N and Datta S 2008 IEEE/ACM Int. Symp. on Nanoscale Architectures Proc. (Anaheim, CA, June 2008) p61
14. Hioe W, Hosoya M, Kominami S, Yamada H, Mita R and Takagi K 1995 IEEE Trans. Appl. Supercond. 5 2992
15. Minato S, Ishiura N and Yajima S 1990 27th ACM/IEEE Design Automation Conf. Proc. (Orlando, FL, June 1990) p52
16. Kuroda T and Sakurai T 1995 IEICE Trans. Electron. E78-C 334
17. Naeemi A, Joshi Y, Fedorov A, Kohl P and Meindl J D 2005 Int. Conf. on Integrated Circuit Design and Technology (Padova, May 2005) p171
18. Yumoto M, Kasai S and Hasegawa H 2005 IOP Conf. Ser. 184 213
19. Zhao H-Q, Kasai S, Hashizume T and Wu N-J 2008 IEICE Trans. Electron. E91-C 1063
20. Kouvwenhoven L P, Johnson A T, van der Vaart N C and Harmans C J P 1991 Phys. Rev. Lett. 67 1626
21. Fujiwara A, Nishiguchi K and Ono Y 2008 Appl. Phys. Lett. 92 042102
22. Kaestner B, Kashcheyevs V, Hein G, Pierz K, Siegner U and Schumacher H W 2008 Appl. Phys. Lett. 92 192106
23. Asahi N, Akazawa M and Amemiya Y 1997 IEEE Trans. Electron Devices 44 1109
24. Yumoto M, Kasai S and Hasegawa H 2002 Appl. Surf. Sci. 190 242
25. Kawaura H, Sakamoto T and Baba T 1999 Si Nanoelectronics Workshop Abstracts (Kyoto, June 1999) p26
26. Shiratori Y and Kasai S 2008 Japan J. Appl. Phys. 48 3086
27. Kasai S and Hasegawa H 2001 59th Annual Device Research Conf. (Notre Dame, June 2001) p25
28. Karlström O, Wacker A, Nilsson K, Astromskas G, Roddaro S, Samuelson L and Wernersson L-E 2008 Nanotechnology 19 435201
29. Tomioka K, Mohan P, Noborisaka J, Hara S, Motohisa J and Fukui T 2007 J. Cryst. Growth 298 644
30. Dick K A, Deppert K, Karlsson L S, Seifert W, Wallenberg L R and Samuelson L 2006 Nano Lett. 6 2842
31. Kasai S and Asai T 2008 Appl. Phys. Express 1 083001
32. Kasai S 2009 Int. J. Nanotech. Mol. Comput. 1 70
33. Shiells R A and Falk G 2002 J. Physiol. 542.1 211
34. Soeleman H and Roy K 1999 Proc. 1999 Int. Symp. on Low Power Electronics and Design (San Diego, CA, Aug. 1999) p94
35. International Technology Roadmap for Semiconductors available at http://www.itrs.net 2007