A 65 nm test structure for SRAM device variability and NBTI statistics

Solid-State Electronics

Volumn 53, Issue 7, 2009, Pages 773-778

  Fischer, Thomas ^a   Amirante, Ettore ^b   Huber, Peter ^b   Hofmann, Karl ^b   Ostermayr, Martin ^b   Schmitt Landsiedel, Doris ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

NBTI; SRAM; Test structure; Variability

Indexed keywords

6T-SRAM; GAUSSIAN DISTRIBUTED; MOS TRANSISTORS; NBTI; NEGATIVE BIAS TEMPERATURE INSTABILITY; PROBABILITY DENSITY FUNCTION (PDF); SRAM; STANDARD DEVIATION; STATIC NOISE MARGIN; TEST STRUCTURE; TRANSISTOR PARAMETERS; VARIABILITY;

DRAIN CURRENT; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; PROBABILITY DENSITY FUNCTION; STATIC RANDOM ACCESS STORAGE; TESTING; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

THERMODYNAMIC STABILITY;

EID: 67349194351     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.02.012     Document Type: Article

References (11)

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