A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Volumn , Issue , 2008, Pages 51-54

  Fischer, Thomas ^a   Amirante, Ettore ^b   Hofmann, Karl ^b   Ostermayr, Martin ^b   Huber, Peter ^b   Schmitt Landsiedel, Doris ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTION FUNCTIONS; DRAIN CURRENT; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; NETWORKS (CIRCUITS); PROBABILITY DENSITY FUNCTION; PROBABILITY DISTRIBUTIONS; STATIC RANDOM ACCESS STORAGE; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS; TRELLIS CODES;

GAUSSIAN; MOS TRANSISTORS; NEGATIVE BIAS TEMPERATURE INSTABILITIES; PROBABILITY DENSITIES; SRAM CELLS; STANDARD DEVIATIONS; STATIC NOISE MARGINS; STATISTICAL VARIATIONS; TEST STRUCTURES; TRANSISTOR PARAMETERS;

THERMODYNAMIC STABILITY;

EID: 58049090504     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2008.4681696     Document Type: Conference Paper

References (11)

1. T. Fischer, C. Otte, D. Schmitt-Landsiedel, E. Amirante, A. Olbrich, P. Huber, M. Ostermayr, T. Nirschl, and J. Einfeld, "A 1 Mbit SRAM test structure to analyze local mismatch beyond 5 sigma variation," Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on, pp. 63-66, March 2007.
2. G. L. Rosa, N. W. Loon, S. Rauch, R. Wong, and J. Sudijono, "Impact of NBTI Induced Statistical Variation to SRAM Cell Stability," IEEE IRPS Proceedings, pp. 274-282, 2006.
3. K. Kang, S. P. Park, K. Roy, and M. A. Alam, "Estimation of Statistical Variation in Temporal NBTI Degradation and its Impact on Lifetime Circuit Performance," IEEE ICCAD, pp. 730-734, 2007.
4. K. O. Jeppson and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices," J. Appl. Phys., vol. 48, no. 5, pp. 2004-2014, May 1977.
5. A. Haggag, G. Anderson, S. Parihar, D. Burnett, G. Ablen, J. Higman, and M. Moosa, "Understanding SRAM High-Temperature-Operating-Life NBTI: Statistics and Permanent vs Recoverable Damage," IEEE IRPS Proceedings, pp. 452-456, 2007.
6. K. Kang, H. Kufluoglu, K. Roy, and M. A. Alam, "Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis," IEEE Trans. Computer-Aided Design, vol. 26, no. 10, pp. 1770-1781, October 2007.
7. Y. Wang, "Effects of Interface States and Positive Charges on NBTI in Silicon-Oxynitride p-MOSFETs," IEEE Trans. Device Mat. Ret., vol. 8, no. 1, pp. 14-21, March 2008.
8. H. Reisinger, O. Blank, W. Henrings, W. Gustin, and C. Schlünder, "A comparison of very fast to very slow components in degradation and recovery due to NBTI and bulk hole trapping to existing physical models," IEEE Trans. Device Mat. Ret., vol. 7, no. 1, pp. 119-129, March 2007.
9. S. Rauch, "Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations," IEEE Trans. Device Mat. Ret., vol. 7, no. 4, pp. 524-530, Dec 2007.
10. M. Agostinelli, S. Lau, S. Pae, P. Marzolf, H. Muthali, and S. Jacobs, "PMOS NBTI-induced circuit mismatch in advanced technologies," IEEE IRPS Proceedings, pp. 171 - 175, 2007.
11. E. Seevinck, F. J. List, and J. Lohstroh, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Trans. Syst. Sci. Cybernetics, vol. 22, no. 5, pp. 748-754, October 1987.