PMOS NBTI-induced circuit mismatch in advanced technologies

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 171-175

  Agostinelli, M ^a   Lau, S ^a   Pae, S ^a   Marzolf, P ^b   Muthali, H ^b   Jacobs, S ^a  

^a Technology Development Q and R   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CMOS INTEGRATED CIRCUITS;

90NM TECHNOLOGIES; ADVANCED TECHNOLOGY; ANALOG APPLICATIONS; CIRCUIT MISMATCH; CMOS TECHNOLOGY; NEGATIVE BIAS TEMPERATURE INSTABILITY; PMOS TRANSISTORS; PROCESS VARIATION;

INTEGRATED CIRCUITS;

EID: 25844479977     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315319     Document Type: Conference Paper

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8. J. Bastos, IEEE Journ of Solid State Circuits, v33, n12,1998