On the limitations of silicon for I-MOS integration

IEEE Transactions on Electron Devices

Volumn 56, Issue 5, 2009, Pages 1110-1117

  Savio, Andrea ^a,b   Monfray, Stephane ^a   Charbuillet, Clément ^a   Skotnicki, Thomas ^a  

^a STMICROELECTRONICS   (France)

^b INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

Abrupt subthreshold slope; Avalanche breakdown voltage; Germanium; Impact ionization MOS (I MOS) transistor; Silicon

Indexed keywords

ABRUPT SUBTHRESHOLD SLOPE; AVALANCHE BREAKDOWN VOLTAGE; IMPACT IONIZATION MOS; IMPACT IONIZATION MOS (I-MOS) TRANSISTOR; SIMULATIONS AND MEASUREMENTS; SUPPLY VOLTAGES;

ELECTRIC BREAKDOWN; ELECTRIC CONDUCTIVITY; GERMANIUM; IMPACT IONIZATION; IONIZATION OF GASES; SEMICONDUCTING SILICON; TRANSISTORS;

MOS DEVICES;

EID: 67349138182     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2015163     Document Type: Article

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