On the performance limit of impact-ionization transistors

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 117-120

  Shen, C ^a   Lin, J Q ^a   Toh, E H ^a   Chang, K F ^b   Bait, P ^b   Heng, C H ^a   Samudra, G S ^a   Yeo, Y C ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CIVIL AVIATION; COMMERCE; ELECTRON DEVICES; IMPACT IONIZATION; IONIZATION; LASER PULSES; LEAKAGE CURRENTS; NONMETALS; RANDOM PROCESSES; SEMICONDUCTING SILICON; SILICON; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

CARRIER MULTIPLICATION; CMOS DEVICES; IMPACT-IONIZATION MOS; LEAKAGE CONSTRAINTS; MONTE-CARLO SIMULATIONS; OFF-STATE LEAKAGE CURRENT; RANDOM DELAYS; SWITCH-ON; SWITCHING DELAYS; TRANSISTOR SWITCHING;

MOS DEVICES;

EID: 50249171228     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418878     Document Type: Conference Paper

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