Demonstration of full field patterning of 32 nm test chips using EUVL

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7271, Issue , 2009, Pages

  Vandentop, Gilroy ^a   Chandhok, Manish ^a   Putna, Emisse S ^a   Younkin, Todd R ^a   Clarke, James S ^a   Carson, Steven ^a   Myers, Alan ^a   Leeson, Michael ^a   Zhang, Guojing ^a   Liang, Ted ^a   Murachi, Tetsunori ^a  

^a INTEL CORPORATION   (United States)

Author keywords

32 nm; ADT; Defects; EUV lithography; Photoresist

Indexed keywords

32 NM; 32-NM NODE; ADT; DESIGN RULES; EUV LITHOGRAPHY; FULL-FIELD; HIGH VOLUME MANUFACTURING; IMAGING PROCESS; MASK DEFECTS; MASK PATTERNS; PATTERNING PROCESS; PROCESS FLOWS; PROCESS WINDOW; REFLECTIVE OPTICS; TEST CHIPS;

DEFECTS; MASKS; PHOTORESISTORS; SURFACE TREATMENT; TESTING; ULTRAVIOLET DEVICES;

EXTREME ULTRAVIOLET LITHOGRAPHY;

EID: 67149140516     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.814436     Document Type: Conference Paper

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