ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2008, Pages 235-241

  Cao, Shuqing ^a   Salman, Akram A ^b   Beebe, Stephen G ^b   Pelella, Mario M ^b   Chun, Jung Hoon ^c   Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c Sungkyunkwan University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BULK SUBSTRATES; DEVICE DESIGN; ESD PROTECTION DEVICES; FIELD-EFFECT; GATED DIODES; HIGH SPEED I/O; SOI TECHNOLOGY; TEST METHOD; TRANSMISSION LINE PULSE; WORK FOCUS;

DIODES; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; MOS DEVICES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 66649085199     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

1. J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd Edition. Norwell, Massachusetts, USA: Kluwer Academic Publishers, 2004
2. S. Cristoloveanu and S. Li, Electrical Characterization of Silicon-on-Insulator Materials and Devices. Norwell, Massachusetts, USA: Kluwer Academic Publishers, 1995
3. K. Bernstein and N. Rohrer, SOI Circuit Design Concepts. Norwell, Massachusetts, USA: Kluwer Academic Publishers, 2000
4. A. Marshall and S. Natarajan, SOI Design: Analog, Memory and Digital Techniques. Norwell, Massachusetts, USA: Kluwer Academic Publishers,2002
5. G. Shahidi, "SOI Technology for the GHz Era",2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical Papers, pp. 11-14, 2001
6. M. Pelella and J. Fossum, "On the Performance Advantage of PD/SOI CMOS With Floating Bodies", IEEE Transactions on Electron Devices, Vol. 49, No. 1, pp. 96-104, January 2002 (Pubitemid 34504286)
7. S. Voldman, R. Schulz, J. Howard, V. Gross, S. Wu, A. Yapsir, D. Sadana, H. Hovel, J. Walker, F. Assaderaghi, B. Chen, J. Y-C Sun, and G. Shahidi, "CMOS-On-SOI ESD Protection Networks," Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, pp. 291-301, 1996
8. A. Salman, S. Beebe, M. Pelella, and G. Gilfeather, "SOI Lateral Diode Optimization for ESD Protection in 130nm and 90nm Technologies," Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, pp. 421-427, 2005
9. V. Chen, A. Salman, S. Beebe, E. Rosenbaum, S. Mitra, C. Putnam, and R. Gauthier, "SOI Poly-defined Diode for ESD Protection in High Speed I/Os", Proceedings of the International Reliability Physics pp. 635-636, 2006 (Pubitemid 46964598)
10. M. Pelella, G. Burbach, A. Salman, S. Beebe, D. Chan, and J. Buller, "A Novel Self-aligned substratediode International SOI Conference Proceedings, pp. 169- 170, 2005
11. A. Salman, S. Beebe, and M. Pelella, "Double Well Field Effect Diode: Lateral SCR-like Device for ESD Protection of I/Os in Deep Sub-micron SOI", Proceedings of the Electrical verstress/Electrostatic Discharge (EOS/ESD) Symposium EOS/ESD, pp.185-191, 2007
12. ESD Association, Very Fast Transmission Line Pulse (VF-TLP) Standard Practice (SP) Document: "ANSI/ESD SP5.5.2-2007, Electrostatic Discharge Sensitivity Testing - Very Fast Transmission Line VF-TLP) - Component Level"
13. Narasimha et al , "High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-K BEOL, and Immersion Lithography", International Electron Devices Meeting (IEDM) Proceedings, pp. 1-4,2006
14. TSUPREM-4 Manual, Avanti Corp., 2000
15. MEDICI Manual, Avanti Corp., 2000
16. Start-Hspice manual, Avanti Corp, 1998
17. E. Worley, A. Bakulin, "Optimization of Input Protection Diode for High Speed Applications", Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, pp. 62-72, 2002
18. K. Bhatia and E. Rosenbaum, "Layout Guidelines for Optimized ESD Protection Diodes", Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, pp. 19-27, 2007
19. T. Maloney and N. Khurana, "Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena", Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, pp. 49-54, 1985 (Pubitemid 17541002)
20. ESD Association, Transmission Line Pulse (TLP) Standard Practice (SP) Document: "ANSI/ESD SP5.5.1-2005, Electrostatic Discharge Sensitivity Testing - Transmission Line Pulse (TLP) -Component Level"
21. S. Mitra, C. Putnam, R. Gauthier, R. Halbach, C. Seguin, and A. Salman, "Evaluation of ESD Characteristics for 65nm SOI Technology", Proceedings of the International SOI Conference, pp.21-23, 2005 (Pubitemid 43820983)
22. G. Boselli, J. Rodrigeuz, C. Duvvury, and J.Smith, "Analysis of ESD Protection Conponents in 65nm CMOS Technology: Scaling Perspective and Impact on ESD Design Window", Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium EOS/ESD Symposium, pp.43-52, 2005
23. S. Mitra, R. Gauthier, A. Salman, C. Putnam, S.Beebe, R. Halbach, and C. Seguin, "I/O Architecture For Improved ESD Protection In Deep Sub-Micron SOI Technologies", Proceedings of the International SOI Conference, pp.37-38, 2006