On the performance advantage of PD/SOI CMOS with floating bodies

IEEE Transactions on Electron Devices

Volumn 49, Issue 1, 2002, Pages 96-104

  Pelella, Mario M ^a,b,c   Fossum, Jerry G ^a,b  

^a IEEE   (United States)

^b University of Florida   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

CMOS technology scaling; Floating body effects; SOI CMOS

Indexed keywords

CAPACITIVE COUPLING EFFECTS; CIRCUIT SIMULATIONS; FLOATING BODY EFFECTS; KINK EFFECT; PROPAGATION DELAY; STACKED TRANSISTOR LOGIC;

CAPACITANCE; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PERFORMANCE; SILICON ON INSULATOR TECHNOLOGY; TEMPERATURE; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0036247928     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.974755     Document Type: Article

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