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62449290289
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Patterning performance of hyper NA immersion lithography for 32nm node logic process
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Kazuhiro Takahata, Masanari Kajiwara, Yosuke Kitamura, Tomoko Ojima, Masaki Satake, Hiroharu Fujise, Yuriko Seino, Tatsuhiko Ema, Manabu Takakuwa, Shinichiro Nakagawa, Takuya Kono, Masafumi Asano, Suigen Kyo, Akiko Nomachi, Hideaki Harakawa, Tatsuya Ishida, Shunsuke Hasegawa, Katsura Miyashita, Takashi Murakami, Seiji Nagahara, Kazuhiro Takeda, Shoji Mimotogi, and Soichi Inoue, "Patterning performance of hyper NA immersion lithography for 32nm node logic process", Proc. SPIE 7140, 714017 (2008).
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Takahata, K.1
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2
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45449086213
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Immersion resist process for 32-nm node logic devices
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Tatsuhiko Ema, Koutaro Sho, Hiroki Yonemitsu, Yuriko Seino, Hiroharu Fujise, Akiko Yamada, Shoji Mimotogi, Yosuke Kitamura, Satoshi Nagai, Kotaro Fujii, Takashi Fukushima, Toshiaki Komukai, Akiko Nomachi, Tsukasa Azuma, and Shinichi Ito, "Immersion resist process for 32-nm node logic devices", Proc. SPIE 6923, 69230E (2008).
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Ema, T.1
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3
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45449100537
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Patterning strategy and performance of 1.3NA tool for 32nm node lithography
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Shoji Mimotogi, Masaki Satake, Yosuke Kitamura, Kazuhiro Takahata, Katsuyoshi Kodera, Hiroharu Fujise, Tatsuhiko Ema, Koutaro Sho, Kazutaka Ishigo, Takuya Kono, Masafumi Asano, Kenji Yoshida, Hideki Kanai, Suigen Kyoh, Hideaki Harakawa, Akiko Nomachi, Tatsuya Ishida, Katsura Miyashita, and Soichi Inoue, "Patterning strategy and performance of 1.3NA tool for 32nm node lithography", Proc. SPIE 6924, 69240M (2008).
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Mimotogi, S.1
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4
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64549106031
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A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-K process
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S. Hasegawa, Y. Kitamura, K. Takahata, H. Okamoto, T. Hirai, K. Miyashita, T. Ishida, H. Aizawa, S. Aota, A. Azuma, T. Fukushima, H. Harakawa, E. Hasegawa, M. Inohara, S. Inumiya, T. Ishizuka, T. Iwamoto, N. Kariya, K. Kojima, T. Komukai, N. Matsunaga, S. Mimotogi, S. Muramatsu, K. Nagatomo, S. Nagahara. Nakahara, K. Nakajima, K. Nakatsuka, M. Nishigoori, A. Nomachi, R. Ogawa, N. Okada, S. Okamoto, K. Okano, T. Oki, H. Onoda, T. Sasaki, M. Satake, T. Suzuki, Y. Suzuki, M. Tagami, K. Takeda, M. Tanaka, K. Taniguchi, M. Tominaga, G. Tsutsui, K. Utsumi, S. Watanabe, T. Watanabe, Y. Yoshimizu, T. Kitano, H. Naruse, Y. Goto, T. Nakayama, N. Nakamura and F. Matsuoka, "A Cost-Conscious 32nm CMOS Platform Technology with Advanced Single Exposure Lithography and Gate-First Metal Gate/High-K Process", Proc.IEDM2008, p.938 (2008).
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33745780501
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Experimental evaluation of Bulls-Eye illumination for assist-free, random contact printing at sub-65nm node
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DOI 10.1117/12.659420, Optical Microlithography XIX
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[6] Jo Finders, Andre Engelen, Geert Vandenberghe, Joost Bekaert, and Tim Chen, " Experimental evaluation of BullsEye illumination for assist-free random contact printing at sub-65nm node", Proc. SPIE 6154, 615412 (2006). (Pubitemid 44021043)
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35148817491
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The random contact hole solutions for future technology nodes
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Alek Chen, Steve Hansen, Marco Moers, Jason Shieh, Andre Engelen, Koen van Ingen Schenau, and Shih-en Tseng, "The random contact hole solutions for future technology nodes", Proc. SPIE 6520, 65201B (2007).
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