Patterning performance of hyper NA immersion lithography for 32nm node logic process

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7140, Issue , 2008, Pages

  Takahata, Kazuhiro ^a   Kajiwara, Masanari ^a   Kitamura, Yosuke ^a   Ojima, Tomoko ^a   Satake, Masaki ^a   Fujise, Hiroharu ^a   Seino, Yuriko ^a   Ema, Tatsuhiko ^a   Takakuwa, Manabu ^a   Nakagawa, Shinichiro ^a   Kono, Takuya ^a   Asano, Masafumi ^a   Kyo, Suigen ^a   Nomachi, Akiko ^a   Harakawa, Hideaki ^a   Ishida, Tatsuya ^a   Hasegawa, Shunsuke ^a   Miyashita, Katsura ^a   Murakami, Takashi ^b   Nagahara, Seiji ^b   Takeda, Kazuhiro ^b   Mimotogi, Shoji ^a   Inoue, Soichi ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

32nm node; Low kl lithography; RET; Single exposure

Indexed keywords

32NM NODES; 32NM-NODE; ANNULAR ILLUMINATIONS; CONTACT HOLES; EMBEDDED SRAM; EXPOSURE CONDITIONS; FOCUS WINDOWS; HYPER-NA; ILLUMINATION CONDITIONS; IMAGE CONTRASTS; IMMERSION LITHOGRAPHIES; LINE END SHORTENINGS; LINE PATTERNS; LITHOGRAPHY PROCESS; LOGIC PROCESS; LOW-KL LITHOGRAPHY; RESIST PATTERN COLLAPSE; RESONANCE ENHANCEMENTS; RET; SINGLE EXPOSURE; TWO-DIMENSIONAL PATTERNS;

LOGIC DEVICES; NANOTECHNOLOGY; PHOTORESISTS; STATIC RANDOM ACCESS STORAGE; TWO DIMENSIONAL;

LITHOGRAPHY;

EID: 62449290289     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.804739     Document Type: Conference Paper

References (8)

1. S. Mimotogi et al., "Patterning Strategy and Performance of 1.3NATool for 32nm Node Lithography", SPIE Vol. 6924,21(2008)
2. F. Uesawa et al., "Lithography of choice for the 45-nm node: new medium, new wavelength, or new beam?" SPIE Vol. 5377, 34(2004)
3. S.Mimotogi et al., "Optical Lithography Technologies for 45nm-Node CMOS", SPIE Vol.5754, 196(2005)
4. S.Mimotogi et al., "Performance of Immersion Lithography for 45nm-node CMOS and Ultra-High Density SRAM with 0.25um2", SPIE Vol.6520-8(2007)
5. Kohji Hashimoto et al., "ArF Lithography Technologies for 65nm-node CMOS (CMOS5) with 30nm Logic Gate andHigh Density Embedded Memories", Proc. of VLSI symposium 2003, 4B-2
6. B.J.Lin, "The k3 coefficient in nonparaxial scaling equation for resolution, depth of focus, and immersion lithography", JM3-Journal of Microlithography, Microfabrication, and Microsystems 2002,1(1):7 - 12.
7. T.Ema, "Immersion resist process for 32-nm node logic devices", SPIE Vol.6923-13(2008)
8. Y.Seino, "Sub-45-nm resist process using stacked-mask process", SPIE Vol.6923-106(2008)