Immersion resist process for 32nm node logic devices

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6923, Issue , 2008, Pages

  Ema, Tatsuhiko ^a   Sho, Koutarou ^a   Yonemitsu, Hiroki ^a   Seino, Yuriko ^a   Fujise, Hiroharu ^a   Yamada, Akiko ^a   Mimotogi, Shoji ^a   Kitamura, Yosuke ^a   Nagai, Satoshi ^a   Fujii, Kotaro ^a   Fukushima, Takashi ^a   Komukai, Toshiaki ^a   Nomachi, Akiko ^a   Azuma, Tsukasa ^a   Ito, Shinichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Immersion lithography; Reflectivity control; Single BARC; SMAP (stacked mask process); SOC (spin on carbon); Trilayer

Indexed keywords

DEFORMATION; LOGIC DEVICES; NANOTECHNOLOGY; PHOTOLITHOGRAPHY; PHOTORESISTS; PROGRAMMABLE LOGIC CONTROLLERS; REFLECTION; SPIN DYNAMICS; SUBSTRATES;

IMMERSION LITHOGRAPHY; REFLECTIVITY CONTROL; SINGLE BARC; SMAP (STACKED MASK PROCESS); SOC (SPIN-ON-CARBON); TRILAYER;

PROCESS ENGINEERING;

EID: 45449086213     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.771008     Document Type: Conference Paper

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