A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/ high-K process

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Hasegawa, S ^a   Kitamura, Y ^a   Takahata, K ^a   Okamoto, H ^a   Hirai, T ^b   Miyashita, K ^a   Ishida, T ^a   Aizawa, H ^b   Aota, S ^a   Azuma, A ^a   Fukushima, T ^a   Harakawa, H ^a   Hasegawa, E ^b   Inohara, M ^a   Inumiya, S ^a   Ishizuka, T ^a   Iwamoto, T ^b   Kariya, N ^b   Kojima, K ^a   Komukai, T ^a   Matsunaga, N ^a   Mimotogi, S ^a   Muramatsu, S ^b   Nagatomo, K ^a   Nagahara, S ^b   Nakahara, Y ^b   Nakajima, K ^a   Nakatsuka, K ^a   Nishigoori, M ^a   Nomachi, A ^a   Ogawa, R ^a   Okada, N ^b   Okamoto, S ^a   Okano, K ^a   Oki, T ^a   Onoda, H ^a   Sasaki, T ^a   Satake, M ^a   Suzuki, T ^b   Suzuki, Y ^a   Tagami, M ^a   Takeda, K ^b   Tanaka, M ^b   Tamguchi, K ^b   Tominaga, M ^b   Tsutsui, G ^b   Utsumi, K ^a   Watanabe, S ^b   Watanabe, T ^a   Yoshimizu, Y ^a   Kitano, T ^b   Naruse, H ^a   Goto, Y ^b   Nakayama, T ^a   Nakamura, N ^a   Matsuoka, F ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

45 NM TECHNOLOGIES; DOUBLE PATTERNING; GATE DENSITIES; GATE STACKS; PLATFORM TECHNOLOGIES; SINGLE EXPOSURES; SRAM CELLS; STANDARD CELLS; TOTAL COSTS;

ELECTRIC BATTERIES;

ELECTRON DEVICES;

EID: 64549106031     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796776     Document Type: Conference Paper

References (4)

1. S- Y. Wu et al., IEDM Tech. Dig., p.263, 2007
2. X. Chen et al., Symp. on VLSI Tech., p.88, 2008
3. S. Mimotogi et al., SPIE Advanced Lithography, 6924-21, 2008
4. K. J. Kuhn et al., IEDM Tech. Dig., p.471, 20